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Volumn 29, Issue 11, 1982, Pages 1772-1777

GaAs LSI-Directed MESFET's with Self-Aligned Implantation for n+-Layer Technology (SAINT)

Author keywords

[No Author keywords available]

Indexed keywords

MESFET;

EID: 0020208082     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1982.21025     Document Type: Article
Times cited : (42)

References (18)
  • 3
    • 0018725179 scopus 로고
    • GaAs integrated logic with normally-off MESFETs
    • K. Suyama, H. Kusakawa, and M. Fukuta, “GaAs integrated logic with normally-off MESFETs,” Japan. J. Appl. Phys., vol. 18, Suppl. 18–1, pp. 145–149, 1979.
    • (1979) Japan. J. Appl. Phys. , vol.18 , pp. 145-149
    • Suyama, K.1    Kusakawa, H.2    Fukuta, M.3
  • 4
    • 0019001821 scopus 로고
    • GaAs Gigabit logic circuits using normally-off MESFETs
    • T. Mizutani, N. Kato, S. Ishida, K. Osafune, and M. Ohmori, “GaAs Gigabit logic circuits using normally-off MESFETs,” Electron. Lett., vol. 16, pp. 315–316, 1980.
    • (1980) Electron. Lett. , vol.16 , pp. 315-316
    • Mizutani, T.1    Kato, N.2    Ishida, S.3    Osafune, K.4    Ohmori, M.5
  • 7
    • 0019320389 scopus 로고
    • Planar GaAs normally-off JFET for high speed logic circuits
    • Y. Kato, M. Dohsen, J. Kasahara, and N. Watanabe, “Planar GaAs normally-off JFET for high speed logic circuits,” Electron. Lett., vol. 16, pp. 821–822, 1980.
    • (1980) Electron. Lett. , vol.16 , pp. 821-822
    • Kato, Y.1    Dohsen, M.2    Kasahara, J.3    Watanabe, N.4
  • 11
    • 0020474506 scopus 로고
    • A self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs
    • K. Yamasaki, K. Asai, T. Mizutani, and K. Kurumada, “A self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs,” Electron. Lett., vol. 18, pp. 119–121, 1982.
    • (1982) Electron. Lett. , vol.18 , pp. 119-121
    • Yamasaki, K.1    Asai, K.2    Mizutani, T.3    Kurumada, K.4
  • 12
    • 0018545401 scopus 로고
    • High resolution, steep profile resist patterns
    • J. M. Moran and D. Mayden, “High resolution, steep profile resist patterns,” J. Vac. Sci. Technol., vol. 16, p. 1620, 1980.
    • (1980) J. Vac. Sci. Technol. , vol.16 , pp. 1620
    • Moran, J.M.1    Mayden, D.2
  • 14
    • 84939743099 scopus 로고
    • Reactive ion beam etching-Application to GaAs integrated circuit fabrication
    • K. Yamasaki, K. Asai, and K. Kurumada, “Reactive ion beam etching-Application to GaAs integrated circuit fabrication,” in Proc. of Symp. on Dry Process, pp. 105–112, 1981.
    • (1981) Proc. of Symp. on Dry Process , pp. 105-112
    • Yamasaki, K.1    Asai, K.2    Kurumada, K.3
  • 16
    • 0016497460 scopus 로고
    • Field-effect transistor versus analog transistor (static induction transistor)
    • J. Nishizawa, T. Terasaki, and J. Shibata, “Field-effect transistor versus analog transistor (static induction transistor),” IEEE Trans. Electron Devices, vol. ED-22, pp. 185–197, 1975.
    • (1975) IEEE Trans. Electron Devices , vol.ED-22 , pp. 185-197
    • Nishizawa, J.1    Terasaki, T.2    Shibata, J.3
  • 17
    • 0016569468 scopus 로고
    • The ‘barrier mode’ behavior of a junction FET at low drain currents
    • R. J. Brewer, “The ‘barrier mode’ behavior of a junction FET at low drain currents,” Solid-State Electron., vol. 18, pp. 1013–1017, 1975.
    • (1975) Solid-State Electron , vol.18 , pp. 1013-1017
    • Brewer, R.J.1
  • 18
    • 0342728242 scopus 로고
    • Orientation effect on planar GaAs Schottky barrier field effect transistors
    • C. P. Lee, R. Zucca, and B. M. Welch, “Orientation effect on planar GaAs Schottky barrier field effect transistors,” Appl. Phys. Lett., vol. 37, pp. 311–313, 1980.
    • (1980) Appl. Phys. Lett. , vol.37 , pp. 311-313
    • Lee, C.P.1    Zucca, R.2    Welch, B.M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.