Alpha-Particle-Induced Soft Error Rate in VLSI Circuits

IEEE Transactions on Electron Devices

Volumn 29, Issue 4, 1982, Pages 725-731

  Sai Halasz, George A ^a   Wordeman, Matthew R ^a   Dennard, Robert H ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

EID: 0020114737     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1982.20769     Document Type: Article

References (24)

1. T. C. May and M. H. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-26, no. 1, pp. 2–9, Jan. 1979.
2. D. S. Yaney, J. T. Nelson, and L. L. Vanskike, “Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability,” IEEE Trans. Electron Devices, vol. ED-26, no. 1, pp. 10–15, Jan. 1979.
3. S. Kirkpatrick, “Modeling of diffusion and collection of charge from ionizing radiation,” IEEE Trans. Electron Devices, vol. ED-26, no. 11, pp. 1742–1753, Nov. 1979.
4. J. F. Ziegler and W. A. Lanford, “Effect of cosmic rays on computer memories,” Science, vol. 206, no. 4420, pp. 776–788, Nov. 1979.
5. R. J. McPartland, “Circuit simulations of alpha-particle-induced soft errors in MOS dynamic RAM's,” IEEE J. Solid-State Circuits, vol. SC-16, no. 1, pp. 31–34, Feb. 1981.
6. K. Itoh, R. Hori, H. Masuda, and K. Kamigaki, “A single 5V 64K dynamic RAM,” in IEEE ISSCC Tech. Dig., pp. 228–229, Feb. 1980.
7. T. C. Lo, R. E. Scheuerlein, and R. Tamlyn, “A 64K FET dynamic random access memory: Design considerations and description,” IBM J. Res. Develop., vol. 24, no. 3, pp. 318–327, May 1980.
8. H. H. Chao, R. H. Dennard, M. Y. Tsai, M. R. Wordeman, and A. Cramer, “A 34 µm2 DRAM cell fabricated with a 1 µm single level polycide technology,” IEEE J. Solid-State Circuits, vol. SC-16, no. 5, pp. 499–505, Oct. 1981.
9. K. S. Gray, “Cross-coupled charge-transfer sense amplifier and latch sense scheme for high-density FET memories,” IBM J. Res. Develop., vol. 24, no. 3, pp. 283–290, May 1980.
10. J. M. Hammersley and D. C. Handscomb, Monte Carlo Methods, New York: Wiley, 1964.
11. J. F. Ziegler, Ed., The Stopping and Ranges of Ions in Matter. New York: Pergamon, 1980.
12. G. A. Sai-Halasz and M. R. Wordeman, “Monte Carlo modeling of the transport of ionizing radiation created carriers in integrated circuits,” IEEE Electron Devices Lett., vol. EDL-1, no. 10, pp. 211–213, Oct. 1980.
13. C. M. Hsieh, P. C. Murley, and R. R. O'Brien, “A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices,” IEEE Electron Devices Lett., vol. EDL-2, no. 4, pp. 103–105, Apr. 1981.
14. C. M. Hsieh, P. C. Murley, and R. R. O'Brien, “Dynamics of charge collection from alpha particle tracks in integrated circuits,” in 19-th Annual Proc. Reliability Physics Conf., pp. 38–42 (Orlando, FL, 1981).
15. M. R. Wordeman, unpublished.
16. K. Ohta, K. Yamada, M. Saitoh, H. Shiraki, A. Nakamura, K. Shimizu, and Y. Tarui, “A stacked high capacitor RAM,” in IEEE ISSCC Tech. Dig., pp. 66–67, Feb. 1980.
17. T. I. Kamins and G. T. Fong, “Photosensing arrays with improved spatial resolution,” IEEE Trans. Electron Devices, vol. ED-25, no. 2, pp. 154–159, Feb. 1978.
18. A. F. Tasch, Jr., P. K. Chatterjee, H-S Fu, and T. C. Holloway, “The HI-C RAM cell concept,” IEEE Trans. Electron Devices, vol. ED-25, no. 1, pp. 33–41, Jan. 1978.
19. M. Yamada et al., “Soft error improvement of dynamic RAM with HI-C structure,” in 1980 IEDM Tech. Dig., pp. 578–581.
20. M. J. McNutt, “Buried channel transfer device (CTD) transient radiation hardening using n-p-n structures,” IEEE Trans. Nucl. Sci., vol. NS-27, no. 5, pp. 1138–1342, Oct. 1980.
21. O. Minato, T. Masuhara, T. Sasaki, H. Nakamura, Y. Sakai, T. Yasui, and K. Uchibori, “2K × 8 bit Hi-CMOS static RAM's,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1591–1601, Aug. 1980.
22. R. H. Dennard, G. A. Sai-Halasz, and M. R. Wordeman, “Modeling and control of alpha-particle effects in scaled-down VLSI circuits,” presented at the 1981 VLSI Symp., Hawaii, Sept. 1981.
23. M. R. Wordeman, R. H. Dennard, and G. A. Sai-Halasz, “A buried n-grid for protection against radiation induced charge collection in electronic circuits,” presented at the 1981 IEDM, Washington, DC, Dec. 1981. Also in 1981 IEDM Tech. Dig., pp. 40–43.
24. C. E. Thompson and J. M. Meese, “Reduction of a-particle sensitivity in dynamic semiconductor memories (16K d-RAMS) by neutron irradiation,” in Defects in Semiconductors. New York: North-Holland, 1981.