Completely iterative, pipelined multiplier array suitable for VLSI

IEE Proceedings G: Electronics Circuits and Systems

Volumn 129, Issue 2, 1982, Pages 40-46

  McCanny, J V ^a   McWhirer, J G ^a  

^a DEFENCE SCIENCE AND TECHNOLOGY LABORATORY   (United Kingdom)

Author keywords

Algorithms; Integrated circuits; Multplier array

Indexed keywords

INTEGRATED CIRCUITS;

EID: 0020113032     PISSN: 01437089     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-g-1.1982.0008     Document Type: Article

References (22)

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