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Volumn 29, Issue 3, 1982, Pages 368-376

Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta205 High-Density VLSI Dynamic Memory

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR;

EID: 0020101518     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1982.20711     Document Type: Article
Times cited : (82)

References (45)
  • 1
    • 0002007506 scopus 로고
    • Progress in digital integrated electronics
    • Washington, DC
    • G. E. Moore, “Progress in digital integrated electronics,” in IEDM Dig. Tech. Papers (Washington, DC, 1975), p. 11.
    • (1975) IEDM Dig. Tech. Papers , pp. 11
    • Moore, G.E.1
  • 2
    • 0019074219 scopus 로고
    • 256 kbit dynamic RAM
    • San Francisco, CA also, IEEE J. Solid-State Circuits, vol. SC-15, no. 5, pp. 872–874, Oct. 1980
    • S. Matsue, H. Yamamoto, K. Kobayashi, T. Wada, M. Tameda, and Y. Inagaki, “256 kbit dynamic RAM,” in ISSCC Dig. Tech. Papers (San Francisco, CA, 1980) p. 232; also, IEEE J. Solid-State Circuits, vol. SC-15, no. 5, pp. 872–874, Oct. 1980.
    • (1980) ISSCC Dig. Tech. Papers , pp. 232
    • Matsue, S.1    Yamamoto, H.2    Kobayashi, K.3    Wada, T.4    Tameda, M.5    Inagaki, Y.6
  • 3
    • 0019072599 scopus 로고
    • A 256 K RAM fabricated Mo-poly Si technology
    • Oct. also, T. Mano, K. Takeya, T. Watanabe, N. Ieda, K. Kiuchi, E. Arai, T. Ogawa, and K. Hirata, “A fault tolerant 256 K RAM fabricated with Mo-poly Si technology,” IEEE J. Solid-State Circuits, vol. SC-15, no. 5, pp. 865–872, Oct. 1980
    • T. Mano, K. Takeya, T. Watanabe, K. Kiuchi, T. Ogawa, and K. Hirata, “A 256 K RAM fabricated Mo-poly Si technology,” IEEE J. Solid-State Circuits, vol. SC-15, no. 5, p. 234, Oct. 1980; also, T. Mano, K. Takeya, T. Watanabe, N. Ieda, K. Kiuchi, E. Arai, T. Ogawa, and K. Hirata, “A fault tolerant 256 K RAM fabricated with Mo-poly Si technology,” IEEE J. Solid-State Circuits, vol. SC-15, no. 5, pp. 865–872, Oct. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , Issue.5 , pp. 234
    • Mano, T.1    Takeya, K.2    Watanabe, T.3    Kiuchi, K.4    Ogawa, T.5    Hirata, K.6
  • 5
    • 0018331014 scopus 로고
    • a-particle induced soft errors in dynamic memories
    • T. C. May and M. H. Woods, “a-particle induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-26, no. 1, 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26 , Issue.1
    • May, T.C.1    Woods, M.H.2
  • 8
    • 84939057598 scopus 로고
    • Merged charge memory
    • Washington, DC also, IBM J. Res. Develop., p. 402, Sept. 1977
    • H. S. Lee and W. D. Pricer, “Merged charge memory,” in IEDM Dig. Tech. Papers (Washington, DC, 1976), p. 15; also, IBM J. Res. Develop., p. 402, Sept. 1977.
    • (1976) IEDM Dig. Tech. Papers , pp. 15
    • Lee, H.S.1    Pricer, W.D.2
  • 9
    • 84937994982 scopus 로고
    • Stratified Charge Memory
    • D. Erb, “Stratified Charge Memory,” in ISSCC Dig. Tech. Papers, p. 24, 1978.
    • (1978) ISSCC Dig. Tech. Papers , pp. 24
    • Erb, D.1
  • 10
    • 0018479151 scopus 로고
    • Taper isolated dynamic gain RAM cell
    • P. K. Chatterjee, G. W. Taylor, and M. Malwah, “Taper isolated dynamic gain RAM cell,” IEEE IEDM, Late News 1978; also, P. K. Chatterjee, G. W. Taylor, R.L. Easley, H. S. Fu, and A. F. Tasch, Jr., “A survey of high density dynamic RAM cell concept,” IEEE Trans. Electron Devices, vol. ED-26, no. 6, p. 827, June 1979
    • (1978) IEEE IEDM, Late News
    • Chatterjee, P.K.1    Taylor, G.W.2    Malwah, M.3
  • 12
    • 84939049991 scopus 로고
    • Patent pending
    • K. Ohta and A. Kawaji, Patent 1976, pending.
    • (1976)
    • Ohta, K.1    Kawaji, A.2
  • 13
    • 23544458634 scopus 로고
    • The buried source VMOS dynamic RAM device
    • Washington, DC
    • J. J. Barns, S. N. Shadbe, and F. B. Jenne, “The buried source VMOS dynamic RAM device,” in IEDM Dig. Tech. Papers (Washington, DC, 1978), p. 272.
    • (1978) IEDM Dig. Tech. Papers , pp. 272
    • Barns, J.J.1    Shadbe, S.N.2    Jenne, F.B.3
  • 15
    • 0018059603 scopus 로고
    • Novel high density, stacked capacitor MOS RAM
    • Washington, DC also, M. Koyanagi, Y. Sakai, M. Ishihara, M. Tazunoki, and N. Hashimoto, “A 5-V only 16 kbit stacked-capacitor MOS RAM,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1596–1601, Aug. 1980
    • M. Koyanagi, H. Sunami, N. Hashimoto, and M. Ashikawa, “Novel high density, stacked capacitor MOS RAM,” in IEDM Dig. Tech. Papers (Washington, DC, 1978), p. 348; also, M. Koyanagi, Y. Sakai, M. Ishihara, M. Tazunoki, and N. Hashimoto, “A 5-V only 16 kbit stacked-capacitor MOS RAM,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1596–1601, Aug. 1980.
    • (1978) IEDM Dig. Tech. Papers , pp. 348
    • Koyanagi, M.1    Sunami, H.2    Hashimoto, N.3    Ashikawa, M.4
  • 16
    • 84941523896 scopus 로고
    • Vertical charge coupled devices
    • A. Mohsen, “Vertical charge coupled devices,” in ISSCC Dig. Tech. Papers, p. 152, 1979.
    • (1979) ISSCC Dig. Tech. Papers , pp. 152
    • Mohsen, A.1
  • 20
    • 0017981504 scopus 로고
    • A 64 kbit dynamic MOS RAM
    • June
    • E. Arai and N. Ieda, “A 64 kbit dynamic MOS RAM,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 333–338, June 1978.
    • (1978) IEEE J. Solid-State Circuits , vol.SC-13 , pp. 333-338
    • Arai, E.1    Ieda, N.2
  • 23
    • 84984286764 scopus 로고
    • A 64 K MOS dynamic RAM
    • I. Lee et al., “A 64 K MOS dynamic RAM,” in ISSCC Dig. Tech. Papers, p. 146, 1979.
    • (1979) ISSCC Dig. Tech. Papers , pp. 146
    • Lee, I.1
  • 27
    • 0018006585 scopus 로고
    • 64 K dynamic RAM needs only one 5 volt supply to outstrip 16 K parts
    • Sept. 28 also, L. S. White, N. Hong, D. J. Redwine, and G. R. Mohan Rao, “A 5 V only 64 K dynamic RAM,” in ISSCC Dig. Tech. Papers (San Francisco, CA, FAM 17.6, 1980), pp. 230–231
    • G. R. Mohan Rao and J. Hewkin, “64 K dynamic RAM needs only one 5 volt supply to outstrip 16 K parts,” Electronics, pp. 109–116, Sept. 28, 1979; also, L. S. White, N. Hong, D. J. Redwine, and G. R. Mohan Rao, “A 5 V only 64 K dynamic RAM,” in ISSCC Dig. Tech. Papers (San Francisco, CA, FAM 17.6, 1980), pp. 230–231.
    • (1979) Electronics , pp. 109-116
    • Mohan Rao, G.R.1    Hewkin, J.2
  • 30
    • 84939046363 scopus 로고
    • Single 5 V 64 K RAM with scaled down MOS structure
    • Aug.
    • H. Masuda, R. Hori, Y. Kamigaki, and K. Itoh, “Single 5 V 64 K RAM with scaled down MOS structure,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 672–677, Aug. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , pp. 672-677
    • Masuda, H.1    Hori, R.2    Kamigaki, Y.3    Itoh, K.4
  • 34
    • 0018480070 scopus 로고
    • One device cells for dynamic RAM: A tutorial
    • June
    • V. L. Rideout, “One device cells for dynamic RAM: A tutorial,” IEEE Trans. Electron Devices, vol. ED-26, no. 6, p. 389, June 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26 , Issue.6 , pp. 389
    • Rideout, V.L.1
  • 35
    • 0016572696 scopus 로고
    • Fabrication of a miniature 8 K-bit memory chip using electron beam exposure
    • Nov./Dec.
    • H. N. Yu, R. H. Dennard, T.H.P. Chang, C. M. Osborn, V. Dilonardo, and H. E. Luhn, “Fabrication of a miniature 8 K-bit memory chip using electron beam exposure,” J. Vac. Sci. Technol., vol. 12, no. 6, pp. 1297–1300, Nov./Dec. 1975.
    • (1975) J. Vac. Sci. Technol. , vol.12 , Issue.6 , pp. 1297-1300
    • Yu, H.N.1    Dennard, R.H.2    Chang, T.H.P.3    Osborn, C.M.4    Dilonardo, V.5    Luhn, H.E.6
  • 36
    • 85052433421 scopus 로고
    • A 100 ns 64 k dynamic RAM using redundancy techniques
    • New York WPM 8.3
    • S. S. Daton, P. Wooten, W. Slemmer, and J. Brady, “A 100 ns 64 k dynamic RAM using redundancy techniques,” in ISSCC Dig. Tech. Papers, (New York WPM 8.3, 1981), pp. 84–85.
    • (1981) ISSCC Dig. Tech. Papers , pp. 84-85
    • Daton, S.S.1    Wooten, P.2    Slemmer, W.3    Brady, J.4
  • 37
    • 85068235356 scopus 로고
    • A 34 µ2 dRAM cell fabricated with a 1 µ single level polycide FET technology
    • New York WHPM 12.3
    • H. H. Chao, R. H. Dennard, M. Y. Tsai, M. R. Wordeman, and A. Cramer, “A 34 µ2 dRAM cell fabricated with a 1 µ single level polycide FET technology,” in ISSCC Dig. Tech. Papers, (New York WHPM 12.3, 1981), pp. 152–153.
    • (1981) ISSCC Dig. Tech. Papers , pp. 152-153
    • Chao, H.H.1    Dennard, R.H.2    Tsai, M.Y.3    Wordeman, M.R.4    Cramer, A.5
  • 39
    • 0242703464 scopus 로고
    • Future possibilities of dioptic lenses in microelectronics
    • Devices in Semiconductor Microlithography, II
    • G. Ittner, “Future possibilities of dioptic lenses in microelectronics,” in Proc. Soc. Photo-Optical Instr. Engineers (vol. 100), Devices in Semiconductor Microlithography, II, p. 115, 1977.
    • (1977) Proc. Soc. Photo-Optical Instr. Engineers , vol.100 , pp. 115
    • Ittner, G.1
  • 40
    • 0018771671 scopus 로고
    • Coherent illumination improves step and repeat printing on wafers
    • Devices in Semiconductor Microlithography, IV
    • M. Lacombat and G. M. Dubroeucq, “Coherent illumination improves step and repeat printing on wafers,” in Proc. Soc. Photo-Optical Instr. Engineers (vol. 174), Devices in Semiconductor Microlithography, IV, pp. 28–36, 1979.
    • (1979) Proc. Soc. Photo-Optical Instr. Engineers , vol.174 , pp. 28-36
    • Lacombat, M.1    Dubroeucq, G.M.2
  • 45
    • 0018454951 scopus 로고
    • 1 µ MOSFET VLSI technology: Part VII–Metal silicide interconnection technology–A future perspective
    • B. L. Crowder and S. Zirinsky, “1 µ MOSFET VLSI technology: Part VII–Metal silicide interconnection technology–A future perspective,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, p. 369, 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26 , Issue.4 , pp. 369
    • Crowder, B.L.1    Zirinsky, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.