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Volumn 16, Issue 6, 1981, Pages 729-737

A Bipolar Voltage-Controlled Tunable Filter

Author keywords

[No Author keywords available]

Indexed keywords

TUNABLE FILTERS; VOLTAGE-CONTROLLED FILTERS;

EID: 0019707646     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1981.1051669     Document Type: Article
Times cited : (22)

References (6)
  • 1
    • 85068317993 scopus 로고
    • Fully-integrated high-order NMOS sampled-data ladder filters
    • Feb.
    • D. J. Allstot, R. W. Broderson, and P. R. Gray, “Fully-integrated high-order NMOS sampled-data ladder filters,” in ISSCC Dig. Tech. Papers, Feb. 1978, pp. 82–83.
    • (1978) ISSCC Dig. Tech. Papers , pp. 82-83
    • Allstot, D.J.1    Broderson, R.W.2    Gray, P.R.3
  • 2
    • 0018396999 scopus 로고
    • MOS switched-capacitor filters
    • Jan.
    • R. W. Broderson, P. R. Gray, and D. A. Hodges, “MOS switched-capacitor filters,” Proc. IEEE, vol. 67, pp. 61–74, Jan. 1979.
    • (1979) Proc. IEEE , vol.67 , pp. 61-74
    • Broderson, R.W.1    Gray, P.R.2    Hodges, D.A.3
  • 3
    • 0018053229 scopus 로고
    • Fully integrated analog filters using bipolar-JFET technology
    • Dec.
    • K. S. Tan and P. R. Gray, “Fully integrated analog filters using bipolar-JFET technology,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 814–821, Dec. 1978.
    • (1978) IEEE J. Solid-State Circuits , vol.SC-13 , pp. 814-821
    • Tan, K.S.1    Gray, P.R.2
  • 4
    • 67649119451 scopus 로고
    • A precise four-quadrant multiplier with sub-nano-second response
    • Dec.
    • B. Gilbert, “A precise four-quadrant multiplier with sub-nano-second response,” IEEE J. Solid-State Circuits, vol. SC-3, pp. Dec. 1968.
    • (1968) IEEE J. Solid-State Circuits , vol.SC-3
    • Gilbert, B.1
  • 5
    • 84939351131 scopus 로고
    • Ultralinear transistor configuration under conditions of minimal • power-supply drain current
    • June
    • B. Blesser, “Ultralinear transistor configuration under conditions of minimal • power-supply drain current,” IEEE J. Solid-State Circuits, vol. SC-5, pp. 125–126, June 1970.
    • (1970) IEEE J. Solid-State Circuits , vol.SC-5 , pp. 125-126
    • Blesser, B.1
  • 6
    • 0016592668 scopus 로고
    • A precision trim technique for monolithic analog circuits
    • Dec.
    • G. Erdi, “A precision trim technique for monolithic analog circuits,” IEEE J. Solid State Circuits , vol. SC-10 pp. 412–416, Dec. 1975.
    • (1975) IEEE J. Solid State Circuits , vol.SC-10 , pp. 412-416
    • Erdi, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.