A Retrograde p-Well for Higher Density CMOS

IEEE Transactions on Electron Devices

Volumn 28, Issue 10, 1981, Pages 1115-1119

  Rung, Robert D ^a   Dell'Oca, Conrad J ^a   Walker, Laurence G ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE - VERY LARGE SCALE INTEGRATION;

SEMICONDUCTOR DEVICES, MOS;

EID: 0019622076     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1981.20498     Document Type: Article

References (11)

1. See, for example, news review articles in Electronics, Oct. 23, 1980, Dec. 4, 1980.
2. D. L. Wollesen, “CMOS-LSI—The computer component process of the 80's,” IEEE Computer, vol. 13, 59–67, Feb. 1980.
3. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967.
4. Y. Sakai, T. Masuhara, O. Minato, and N. Hashimoto, “High packing density, high speed CMOS (Hi-CMOS) device technology,” Japan J. Appl. Phys., vol. 18, suppl. 18-1, pp. 73–78.
5. R. S. Payne, W. N. Grant, and W. J. Bertram, “Elimination of latch-up in bulk CMOS,” IEDM'80 paper 10.2, Dec. 8–10, 1980, Washington, DC.
6. A. Aitken, “Comparison of bulk silicon and SOS for VLSI CMOS,” IEDM'80 paper 10.1, Dec. 8–10, 1980, Washington, DC.
7. W. D. Raburn, “A model for the parasitic SCR in CMOS,” IEDM '80 paper 10.3, Dec. 8–10, 1980, Washington, DC.
8. M. Shyam and R. D. Rung, Hewlett-Packard internal publication.
9. T. J. Arnold, Hewlett-Packard internal publication.
10. D. B. Estreich, A. Ochoa, Jr., and R. W. Dutton, “An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process,” IEDM'78 paper 9.7, Dec. 4–6, 1978, Washington, DC.
11. D. B. Estreich, private communication.