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Volumn C-30, Issue 5, 1981, Pages 305-312

Optimal Layout of CMOS Functional Arrays

Author keywords

CMOS circuit design; CMOS functional arrays; computer aided design; design automation; LSI design automation; LSI layout

Indexed keywords

INTEGRATED CIRCUITS;

EID: 0019569142     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1981.1675787     Document Type: Article
Times cited : (137)

References (14)
  • 2
    • 0014980091 scopus 로고
    • Synthesis of networks with a minimum number of negative gates
    • Jan.
    • T. Ibaraki and S. Muroga “Synthesis of networks with a minimum number of negative gates,” IEEE Trans. Comput., vol. C-20, pp. 49–58, Jan. 1971.
    • (1971) IEEE Trans. Comput. , vol.C-20 , pp. 49-58
    • Ibaraki, T.1    Muroga, S.2
  • 3
    • 0015282907 scopus 로고
    • Minimal negative gate networks
    • Jan.
    • K. Nakamura, N. Tokura, and T. Kasami, “Minimal negative gate networks,” IEEE Trans. Comput., vol. C-21, pp. 72–79, Jan. 1972.
    • (1972) IEEE Trans. Comput. , vol.C-21 , pp. 72-79
    • Nakamura, K.1    Tokura, N.2    Kasami, T.3
  • 4
    • 84941479876 scopus 로고
    • A study of current logic design problems, Part 1: Design of diagnosable MOS networks
    • Ph.D. dissertation, Dep. Comput. Sci., Univ. of Illinois, Urbana
    • H. C. Lai, “A study of current logic design problems, Part 1: Design of diagnosable MOS networks,” Ph.D. dissertation, Dep. Comput. Sci., Univ. of Illinois, Urbana, 1976.
    • (1976)
    • Lai, H.C.1
  • 5
    • 84939058682 scopus 로고
    • Silicon-on-sapphire technology produces high-speed single-chip processor
    • Apr.
    • B. E. Forbes, “Silicon-on-sapphire technology produces high-speed single-chip processor,” Hewlett-Packard J., pp. 2–8, Apr. 1977.
    • (1977) Hewlett-Packard J. , pp. 2-8
    • Forbes, B.E.1
  • 6
    • 0345056867 scopus 로고
    • Large scale integration of MOS complex logic: A layout method
    • Dec.
    • A. Weinberger, “Large scale integration of MOS complex logic: A layout method,” IEEE J. Solid-State Circuits, vol. SC-2, pp. 182–190, Dec. 1967.
    • (1967) IEEE J. Solid-State Circuits , vol.SC-2 , pp. 182-190
    • Weinberger, A.1
  • 7
    • 84912228838 scopus 로고
    • Computer-generated IGFET layout using vertically packed Weinberger arrangement
    • Philadelphia, PA
    • D. G. Schweikert, “Computer-generated IGFET layout using vertically packed Weinberger arrangement,” in Dig. IEEE Int. Solid-State Circuits Con f., Philadelphia, PA, 1971, pp. 118–119.
    • (1971) Dig. IEEE Int. Solid-State CircuitsConf , pp. 118-119
    • Schweikert, D.G.1
  • 8
    • 0015068386 scopus 로고
    • Computer-aided preliminary layout of customized MOS arrays
    • June
    • R. P. Larsen, “Computer-aided preliminary layout of customized MOS arrays,” IEEE Trans. Comput., vol. C-20, pp. 512–523, June 1971.
    • (1971) IEEE Trans. Comput. , vol.C-20 , pp. 512-523
    • Larsen, R.P.1
  • 9
    • 84944812525 scopus 로고
    • SLIC-Symbolic layout of integrated circuits
    • June San Francisco, CA
    • D. Gibson and S. Nance, “SLIC-Symbolic layout of integrated circuits,” in Proc. 13th Des. Automat. Conf., San Francisco, CA, June 1976, pp. 434–440.
    • (1976) Proc. 13th Des. Automat. Conf , pp. 434-440
    • Gibson, D.1    Nance, S.2
  • 10
    • 84941478059 scopus 로고
    • Symbolic system for circuit layout and checking
    • “Symbolic system for circuit layout and checking,” in Proc. IEEE Int. Symp. Circuits and Syst., 1977, pp. 436–440.
    • (1977) Proc. IEEE Int. Symp. Circuits and Syst. , pp. 436-440
  • 11
    • 84976717328 scopus 로고
    • Automatic layout of low-cost quick-turnaround random-logic LSI devices
    • June San Francisco, CA
    • A. Feller, “Automatic layout of low-cost quick-turnaround random-logic LSI devices,” in Proc. 13th Des. Automat. Conf., San Francisco, CA, June 1976, pp. 79–85.
    • (1976) Proc. 13th Des. Automat. Conf. , pp. 79-85
    • Feller, A.1
  • 12
    • 84984375012 scopus 로고
    • LTX-A system for the directed automatic design of LSI circuits
    • June San Francisco, CA
    • G. Persky, D. N. Deutsch, and D. G. Schweikert, “LTX-A system for the directed automatic design of LSI circuits,” in Proc. 13th Des. Automat. Conf., San Francisco, CA, June 1976, pp. 399–407.
    • (1976) Proc. 13th Des. Automat. Conf. , pp. 399-407
    • Persky, G.1    Deutsch, D.N.2    Schweikert, D.G.3
  • 14
    • 0003780715 scopus 로고
    • Reading, MA: Addison-Wesley
    • F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1969.
    • (1969) Graph Theory
    • Harary, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.