Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation

IEEE Transactions on Electron Devices

Volumn 27, Issue 8, 1980, Pages 1520-1532

  Greenfield, James A ^a   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS; TRANSISTORS, FIELD EFFECT;

INTEGRATED CIRCUITS;

EID: 0019045194     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1980.20066     Document Type: Article

References (30)

1. B. Hoeneisen and C. A. Mead, “Fundamental limitations in micro-electronics-I. MOS technology,” Solid-State Electron., vol. 15, pp. 819–829, July 1972.
2. R. H. Dennard, F. H. Gaensslen, H-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET's with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, Oct. 1974.
3. R. H. Dennard, F. H. Gaensslen, E. J. Walker, and P. W. Cook, “1 µm MOSFET VLSI technology: Part II-Device designs and characteristics for high-performance logic applications,” IEEE Trans. Electron Devices, vol. ED-26, pp. 325–333, Apr. 1979.
4. L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET's,” Solid-State Electron., vol. 17, pp. 1059–1063, Oct. 1974.
5. G. W. Taylor, “Subthreshold conduction in MOSFET's,” IEEE Trans. Electron Devices, vol. ED-25, pp. 337–350, Mar. 1978.
6. C. Bulucea, A. Rusu, and C. Postolache, “Surface breakdown in silicon planar junctions-A computer-aided experimental determination of the critical field,” Solid-State Electron., vol. 17, pp. 881–888, Sep. 1974.
7. M. Bakowski and B. Hansson, “Influence of bevel angle and surface charge on the breakdown voltage of negatively beveled diffused p-n junctions,” Solid-State Electron., vol. 18, pp. 651–657, July 1975.
8. K. E. Kroell and G. K. Ackermann, “Threshold voltage of narrow channel field effect transistors,” Solid-State Electron., vol. 19, pp. 77–81, Jan. 1976.
9. D. J. Coe, H. E. Brockman, and K. H. Nicholas, “A comparison of simple and numerical two-dimensional models for the threshold voltage of short channel MOSTs,” Solid-State Electron., vol. 20, pp. 993–998, Dec. 1977.
10. R. M. Barsan, “Characteristics of the overlaid charge-coupled device,” IEEE Trans. Electron Devices, vol. ED-26, pp. 123–134, Feb. 1979.
11. A. Rusu and C. Bulucea, “Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors,” IEEE Trans. Electron Devices, vol. ED-26, pp. 201–205, Mar. 1979.
12. P. K. Chatterjee, G. W. Taylor, and A. F. Tasch, Jr., “Charge-coupled device structures for VLSI memories,” IEEE Trans. Electron Devices, vol. ED-26, pp. 871–881, June 1979.
13. D. B. Scott and S. G. Chamberlain, “A calibrated model for the subthreshold operation of a short channel MOSFET including surface states,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 633–644, June 1979.
14. H. W. Loeb, R. Andrew, and W. Love, “Application of 2-dimensional solutions of the Shockley-Poisson equation to inversion layer M.O.S.T. devices,” Electronics Lett., vol. 4, pp. 352–354, Aug. 1968.
15. F. H. De La Moneda, “Threshold voltage from numerical solution of the two-dimensional MOS transistor,” IEEE Trans. Circuit Theory, vol. CT-20, pp. 666–673, Nov. 1973.
16. J. D. Last, D. W. Lucas, and G. W. Sumerling, “A numerical analysis of the d.c. performance of small geometry lateral transistors,” Solid-State Electron., vol. 17, pp. 1111–1118, Nov. 1974.
17. O. Manck and W. L. Engl, “Two-dimensional computer simulation for switching a bipolar transistor out of saturation,” IEEE Trans. Electron Devices, vol. ED-22, pp. 339–347, June 1975.
18. J. J. Barnes, R. L. Lomax, and G. I. Haddad, “Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates,” IEEE Trans. Electron Devices, vol. ED-23, pp. 1042–1048, Sept. 1976.
19. T. Nakamura, M. Yamamoto, H. Ishikawa, and M. Shinoda, “Submicron channel MOSFET's logic under punchthrough,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 572–577, Oct. 1978.
20. T. Toyabe and S. Asai, “Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis,” IEEE Trans. Electron Devices, vol. ED-26, pp. 453–461, Apr. 1979.
21. T. Adachi, A. Yoshii, and T. Sudo, “Two-dimensional semiconductor analysis using finite-element method,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1026–1031, July 1979.
22. E. Demoulin, J. A. Greenfield, R. W. Dutton, P. K. Chatterjee, and A. F. Tasch, Jr., “Process statistics of submicron MOSFET's,” in IEEE Int. Electron Devices Meet., Dig. Tech. Papers, 1979.
23. P. K. Chatterjee, G. W. Taylor, and M. Malwah, “Taper isolated dynamic gain RAM cell,” in IEEE Int. Electron Devices Meet., Dig. Tech. Papers (Late News), 1978.
24. J. A. Greenfield, “Analysis and limitations of MOS devices for VLSI applications,” Ph.D. dissertation, Stanford University, Stanford, CA, to be published.
25. D. A. Antoniadis and R. W. Dutton, “Models for computer simulation of complete IC fabrication process,” IEEE Trans. Electron Devices, vol. ED-26, pp. 490–500, Apr. 1979.
26. H. Runge, “Distribution of implanted ions under arbitrarily shaped mask edges,” Phys. Status Solidi (a), vol. 39, pp. 595–599, 1977.
27. H. G. Lee and R. W. Dutton, “Minimum geometry design considerations using a two-dimensional implantation/diffusion model,” Abstract 552, presented at the Elect. Soc. Fall Meeting, Los Angeles, CA, Oct. 1979.
28. R. S. Varga, Matrix Iterative Analysis. Englewood Cliffs, NJ: Prentice-Hall, 1962, ch. 6.
29. J. M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear Equations in Several Variables. New York: Academic Press. 1970, pp. 214–230.
30. B. A. Carre, “The determination of the optimum accelerating factor for successive over-relaxation,” Comput. J., vol. 4, pp. 73–78, 1961.