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Volumn C-29, Issue 7, 1980, Pages 673-678

Detection of Single Intermittent Faults in Sequential Circuits

Author keywords

deterministic and random testing; Error latency; input probability; intermittent fault; Markov chain; sequential circuit; state table

Indexed keywords

LOGIC CIRCUITS, SEQUENTIAL;

EID: 0019033106     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1980.1675642     Document Type: Article
Times cited : (8)

References (11)
  • 1
    • 0142204059 scopus 로고
    • Effects and detection of intermittent failures in digital systems
    • Montvale, NJ: AFIPS
    • M. Ball and F. Hardie, “Effects and detection of intermittent failures in digital systems,” in 1969 Fall Joint Comput. Conf., AFIPS Conf., Proc., vol. 35. Montvale, NJ: AFIPS, 1969, pp. 329–335.
    • (1969) 1969 Fall Joint Comput. Conf., AFIPS Conf., Proc. , vol.35 , pp. 329-335
    • Ball, M.1    Hardie, F.2
  • 2
    • 0015604808 scopus 로고
    • Testing for intermittent faults in digital circuits
    • Mar.
    • M. A. Breuer, “Testing for intermittent faults in digital circuits,” IEEE Trans. Comput., vol. C-22, pp. 241–246, Mar. 1973.
    • (1973) IEEE Trans. Comput. , vol.C-22 , pp. 241-246
    • Breuer, M.A.1
  • 4
    • 0016080117 scopus 로고
    • Intermittent faults: A model and detection procedure
    • July
    • S. Kamal and C. V. Page, “Intermittent faults: A model and detection procedure,” IEEE Trans. Comput., vol. C-23, pp. 713–719, July 1974.
    • (1974) IEEE Trans. Comput. , vol.C-23 , pp. 713-719
    • Kamal, S.1    Page, C.V.2
  • 7
    • 84947667260 scopus 로고
    • Derivation of optimum test sequences for sequential machines
    • presented at the 5th Ann. Symp. Switching Theory and Logical Design
    • J. F. Poage and E. J. McCluskey, “Derivation of optimum test sequences for sequential machines,” presented at the 5th Ann. Symp. Switching Theory and Logical Design, 1964.
    • (1964)
    • Poage, J.F.1    McCluskey, E.J.2
  • 8
    • 0017635707 scopus 로고
    • Optimal random testing of single intermittent failures in combinational circuits
    • Los Angeles, CA, June
    • J. Savir, “Optimal random testing of single intermittent failures in combinational circuits,” in Dig. 1977 Int. Symp. Fault Tolerant Comput., Los Angeles, CA, June 1977, pp. 180–185.
    • (1977) Dig. 1977 Int. Symp. Fault Tolerant Comput. , pp. 180-185
    • Savir, J.1
  • 9
    • 84939343546 scopus 로고
    • Model and random-testing properties of intermittent faults in combinational circuits
    • July
    • ――, “Model and random-testing properties of intermittent faults in combinational circuits,” J. Design Automat. Fault Tolerant Comput., pp. 15–230, July 1978.
    • (1978) J. Design Automat. Fault Tolerant Comput., pp , pp. 15-230
  • 10
    • 84939032020 scopus 로고
    • Detection of intermittent faults in sequential circuits
    • Digital Systems Lab., Stanford University, Stanford, CA, Tech. Rep. 120, Mar.
    • ――, “Detection of intermittent faults in sequential circuits,” Digital Systems Lab., Stanford University, Stanford, CA, Tech. Rep. 120, Mar. 1978.
    • (1978)
  • 11
    • 0016963933 scopus 로고
    • The error latency of a fault in sequential digital circuit
    • June
    • J. J. Shedletsky and E. J. McCluskey, “The error latency of a fault in sequential digital circuit,” IEEE Trans. Comput., vol. C-25, pp. 655–659, June 1976.
    • (1976) IEEE Trans. Comput. , vol.C-25 , pp. 655-659
    • Shedletsky, J.J.1    McCluskey, E.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.