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Volumn C-29, Issue 1, 1980, Pages 55-59

Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets

Author keywords

Boolean difference; bridging faults; intergate bridging faults; intragate bridging faults; irredundant networks; redundancy; short circuits; two level networks; unate networks; undetectability

Indexed keywords

FAULT DETECTION;

EID: 0018924690     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1980.1675457     Document Type: Article
Times cited : (34)

References (13)
  • 4
    • 0016081302 scopus 로고
    • Diagnosis of short circuit faults in combinational circuits
    • July
    • A. D. Friedman, “Diagnosis of short circuit faults in combinational circuits,” IEEE Trans. Comput., Vol. C-23, 746–752, July 1974.
    • (1974) IEEE Trans. Comput. , vol.C-23 , pp. 746-752
    • Friedman, A.D.1
  • 5
    • 0016080487 scopus 로고
    • Bridging and stuck-at-faults
    • July
    • K. C. Y. Mei, “Bridging and stuck-at-faults,” IEEE Trans. Comput., Vol. C-23, pp. 720–727, July 1974.
    • (1974) IEEE Trans. Comput. , vol.C-23 , pp. 720-727
    • Mei, K.C.Y.1
  • 6
    • 0015564343 scopus 로고
    • Enhancing testability of large-scale integrated circuits via test points and additional logic
    • Jan.
    • M. J. Y. Williams and J. B. Angell, “Enhancing testability of large-scale integrated circuits via test points and additional logic.” IEEE Trans. Comput., Vol. C-22, pp. 46–60, Jan. 1973.
    • (1973) IEEE Trans. Comput. , vol.C-22 , pp. 46-60
    • Williams, M.J.Y.1    Angell, J.B.2
  • 7
    • 84914861595 scopus 로고
    • On the detection of bridge and shorted diode faults
    • Oct. Urbana, IL
    • S. M. Reddy, “On the detection of bridge and shorted diode faults,” in Proc. Allerton Conf., Urbana, IL, Oct. 1974.
    • (1974) Proc. Allerton Conf
    • Reddy, S.M.1
  • 8
    • 0017969062 scopus 로고
    • Optimal detection of bridge faults and stuck-at faults in two-level logic
    • May
    • A. Isoupvicz, “Optimal detection of bridge faults and stuck-at faults in two-level logic,” IEEE Trans. on Computers, Vol. C-27, pp. 452–55, May 1978.
    • (1978) IEEE Trans. on Computers , vol.C-27 , pp. 452-455
    • Isoupvicz, A.1
  • 9
    • 0039607679 scopus 로고
    • Analyzing errors with the Boolean difference
    • July
    • F. F. Sellers, M. Y. Hsiao, and C. L. Bearnson, “Analyzing errors with the Boolean difference,” IEEE Trans. Comput., Vol. C-17, 676–683, July 1968.
    • (1968) IEEE Trans. Comput. , vol.C-17 , pp. 676-683
    • Sellers, F.F.1    Hsiao, M.Y.2    Bearnson, C.L.3
  • 10
    • 2342587244 scopus 로고
    • Fault detection in redundant circuits
    • Feb.
    • A. D. Friedman, “Fault detection in redundant circuits,” IEEE Trans. Electron. Comput., Vol. EC-16, pp. 99–100, Feb. 1967.
    • (1967) IEEE Trans. Electron. Comput. , vol.EC-16 , pp. 99-100
    • Friedman, A.D.1
  • 11
    • 0016129791 scopus 로고
    • On the design of logic networks with redundancy and testability considerations
    • Nov.
    • R. Dandapani and S. M. Reddy, “On the design of logic networks with redundancy and testability considerations,” IEEE Trans. Computers, Vol. C-23, pp. 1139–1149, Nov. 1974.
    • (1974) IEEE Trans. Computers , vol.C-23 , pp. 1139-1149
    • Dandapani, R.1    Reddy, S.M.2
  • 12
    • 0016994352 scopus 로고
    • On properties of irredundant logic networks
    • Sept.
    • J. P. Hayes, “On properties of irredundant logic networks,” IEEE Trans. Comput., Vol. C-25, pp. 884–492, Sept. 1976.
    • (1976) IEEE Trans. Comput. , vol.C-25 , pp. 492-884
    • Hayes, J.P.1
  • 13
    • 0018306488 scopus 로고
    • Design of self-checking MOS-LSI circuits, application to a four-bit microprocessor
    • June Madison, WI
    • Y. Crouzet and C. Landrault, “Design of self-checking MOS-LSI circuits, application to a four-bit microprocessor,” in Proc. FTC-9, Madison, WI, pp. 189–192, June 1979.
    • (1979) Proc. FTC-9 , pp. 189-192
    • Crouzet, Y.1    Landrault, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.