Ballistic Transport in Semiconductor at Low Temperatures for Low-Power High-Speed Logic

IEEE Transactions on Electron Devices

Volumn 26, Issue 11, 1979, Pages 1677-1683

  Eastman, Lester F ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR MATERIALS;

EID: 0018545753     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1979.19671     Document Type: Article

References (7)

1. J. Ballantyne “The electronic revolution and the potential of the new submicron facility at Cornell, Engineering,” Cornell Quart., vol. 12, no. 4, pp. 2–11, Apr. 1978.
2. H. Rees, G. S. Sanghera, and R. A. Warriner “Low temperature F.E.T. for low-power high-speed logic,” Electron. Lett., vol. 13, no. 6, pp. 156–158, 1977.
3. R. W. Hockney, R. A. Warriner, and M. Reiser “Two dimensional particle models in semiconductor-device analysis,” Electron. Lett., vol. 10, pp. 484–486, 1974.
4. M. S. Shur “Influence of non-uniform field distribution in the channel on the frequency performance of GaAs FET's,” Electron. Lett., vol. 12, pp. 615–616, 1976.
5. D. J. Herrel “Femtojoule Josephson tunneling logic gates,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 277–282, 1974.
6. R. L. Van Tuyl and C. A. Liechti “High speed integrated logic with GaAs MESFETs,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 269–276, 1974.
7. B. M. Welch and R. Eden, “Planar GaAs integrated circuits fabricated by ion implantation,” in Tech. Dig. 1977 Int. Electron Devices Meet. (Washington, DC), pp. 205–208.