Techniques for The Simulation of Large-Scale Integrated Circuits

IEEE Transactions on Circuits and Systems

Volumn 26, Issue 9, 1979, Pages 741-749

  Newton, A Richard ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING;

INTEGRATED CIRCUITS;

EID: 0018524019     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1979.1084694     Document Type: Article

References (15)

1. L. W. Nagel, “SPICE2, A computer program to simulate semiconductor circuits,” University of California, Berkeley, ERL Memo No. ERL-M520, May 1975.
2. G. R. Case, “SALOGS—A CDC 6600 program to simulate digital logic networks, vol. 1—User’s manual,” Sandia Lab Rep. SAND 74–0441, 1975.
3. P. Wilcox and A. Rombeck, “F/LOGIC—An interactive fault and logic simulator for digital circuits,” Proc. 13th Design Automation Conf., pp. 68–73, 1976.
4. Several large-scale logic and fault analysis simulators are commer-cially available, such as CC-TEGAS3, D-LASAR, and LOGCAP.
5. B. R. Chawla, H. K. Gununel, and P. Kozak, “MOTIS—An MOS timing simulator,” Trans. IEEE, vol. CAS-22, pp. 901–909, Dec. 1975.
6. S. P. Fan, M. Y. Hsueh, A. R. Newton, and D. O. Pederson, “MOTIS-C: A new circuit simulator for MOS LSI circuits,” Proc. IEEE mt. Symp. Circuits Syst., pp. 700–703, Apr. 1977.
7. G. R. Boyle, “Simulation of integrated injection logic,” University of California, Berkeley, ERL Memo No. ERL-M78/13, Mar. 1978.
8. M. Y. Hsueh, A. R. Newton, and D. O. Pederson, “New approaches to modeling and electrical simulation of LSI logic circuits,” Journees d’Electronique, pp. 403–413, Lausanne, Switzer-land, 1977.
9. G. Arnout, H. De Man, “The use of threshold functions and boolean-controlled network elements for macromodelling of LSI circuits,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 326–332, June 1978.
10. N. B. Rabbat and H. Y. Hsieh, “A latent macromodular approach. to large-scale sparse networks,‘’ IEEE Trans., Circuits Syst., vol. CAS-23, pp. 745–752, Dec. 1976.
11. L. O. Chua and P. M. Lin, Computer Aided Analysis of Electronics circuits: Algorithms and computational Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1975.
12. S. A. Szygenda and E. W. Thompson, “Modeling and digital simulation for design verification and diagnosis,” IEEE Trans. Computers, vol. C-25, pp. 1242–1253, Dec. 1976.
13. A. It. Newton and D. O. Pederson, “Analysis time, accuracy and memory requirement tradeoffs in SPICE2, 11 th Asilomar Conf. Circuits Syst. and Computers, (Asilomar, CA) pp. 6–9, Nov. 1977.
14. A. R. Newton, “The simulation of large-scale integrated circuits,” University of California, Berkeley, ERL Memo No. ERL-M78/52, July 1978.
15. J. M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear Equations in Several Variables. New York: Academic, 1970.