An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure

IEEE Transactions on Electron Devices

Volumn 26, Issue 4, 1979, Pages 576-586

  Guterman, Daniel C ^a   Rimawi, Isam H ^a   Chiu, Te Long ^a   Halvorson, Richard D ^a   McElroy, David J ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PROCESSING, SEMICONDUCTOR;

EID: 0018454998     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1979.19462     Document Type: Article

References (63)

1. W. M. Gosney, “DIFMOS-A floating-gate electrically erasable nonvolatile semiconductor memory technology,” IEEE Trans. Electron Devices, vol. ED-24, pp. 594–599, May 1977.
2. J. W. Kelly and D. F. Millet, “An electrically alterable ROM—And it doesn’t use nitride,” Electronics, pp. 101–104, Dec. 1976.
3. R. G. Miller, H. Nietsch, B. Rossler, and E. Wolter, “An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 507–514, Oct. 1977.
4. E. Harari, L. Schmite, B. Troutman, and S. Wang, “A 256-bit nonvolatile static RAM,” in 1978 Int. Solid State Circuits Conf. Tech. Digest, pp. 108–109, Feb. 1978.
5. See, for example, Texas Instruments Data Sheet MOS LSI TMS2516JL and TMS2532JL 16K and 32K EPROMS, Apr. 1978.
6. H. R. Huff, R. Halvorson, T. L. Chiu, and D. Guterman, submitted to Fall 1978 Electrochemical Society Meet.
7. D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable FAMOS read-only memory,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 301–306, Oct. 1971.
8. J. J. Barnes, J. L. Linden, and J. R. Edwards, “Operation and characterization of n-channel EPROM cells,” in Int. Electron Devices Meet. Digest Tech. Papers, p. 173, Dec. 1976.
9. H. Shichman and D. A. Hodges, IEEE J. Solid-State Circuits, vol. SC-3, pp. 285–289, Sept. 1968.
10. F. F. Fang and A. B. Fowler, “Hot electron effects and saturation velocities in silicon inversion layers,” J. Appl. Phys., vol. 41, pp. 1825–1831, Mar. 1970.
11. H. Kroemer, “Hot-electron relaxation effects in devices,” Solid-State Electron., vol. 21, pp. 61–67, 1978.
12. T. H. Ning, “Hot-electron emission from silicon into silicon dioxide,” Solid-State Electron.,vol. 21, pp. 273–282, 1978.
13. R. R. Troutman, “Silicon surface emission of hot electrons,” Solid-State Electron., vol. 21, pp. 283–289, 1978.
14. S. M. Sze, Physics of Semiconductor Devices, New York: Wiley, 1969, ch. 6.
15. 2” J. Appl. Phys., vol. 45, pp. 5373–5378, Dec. 1974.
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17. S. A. Abbas and C. A. Barile, “P-channel rewritable avalanche injection device (RAID) operation and degradation mechanisms,” in 13th Annu. Proc. Reliability Physics (Las Vegas, NV, vol. 13, 1976), pp. 1–5.
18. 2” J. Appl. Phys., vol. 40, pp. 278–283, Jan. 1969.
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20. D. J. DiMaria and D. R. Kerr, “Interface effects and high conductivity in oxides grown from poly crystalline silicon,” Appl. Phys. Lett., vol. 27, pp. 505–507, Nov. 1975.
21. H. Iizuka, F. Masuoka, T. Sato, and M. Ishikawa, “Electrically alterable avalanche-injection-type MOS read-only memory with stacked-gate structure,” IEEE Trans. Electron Devices, vol. ED-23, pp. 379–387, Apr. 1976.
22. D. R. Kerr, “Mechanism of conduction in oxide growth on poly crystalline silicon,” Electrochemical Society Extended Abstracts (Oct. 1976), pp. 839–-841.
23. R. A. Anderson and D. R. Kerr, “Evidence for surface asperity mechanism of conductivity in oxide grown on poly crystalline silicon,” J. Appl. Phys., vol. 48, pp. 4834–4836, Nov. 1977.
24. T. I. Kamins and E. L. MacKenna, “Thermal oxidation of polycrystalline silicon films,” Metallurgical Trans., vol. 2, pp. 2244–2292, Aug. 1971.
25. D. K. Schroder and R. N. Thomas, “Experimental confirmation of the Fowler-Nordheim law for large-area field emitter arrays,” Appl. Phys. Lett., vol. 23, pp. 15–16, July 1973.
26. D. J. DiMaria, D. R. Young, and D. W. Ormond, “Use of electron-trapping region to reduce leakage currents and improve break-down characteristics of MOS structures,” Appl. Phys. Lett., vol. 31, pp. 680–682, Nov. 1977.
27. 2” J. Electrochem. SocSolid-State ScL Technovol. 123, pp. 42–47, Jan. 1976.
28. T. W. Hickmott, “Annealing of surface states in polycrystelline-silicon-gate capacitors,” J. Appl. Phys., vol. 48, pp.723–733 Feb. 1977.
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31. R. H. Walden, “A method for the determination of high-field conduction laws in insulating films in the presence of tra.)ped pped charge,” vol. 43, pp. 1178–1186, Mar. 1972.
32. W. M. Gosney, “DIFMOS-A floating-gate electrically erasable nonvolatile semiconductor memory technology,” IEEE Trans. Electron Devices, vol. ED-24, pp. 594–599, May 1977.
33. J. W. Kelly and D, F. Millet, “An electrically alterable ROM—And it doesn’t use nitride,” Electronics, pp. 101–104, Dec. 1976.
34. R. G. Miller, H. Nietsch, B. Rossler, and E. Wolter, “An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 507–514, Oct. 1977.
35. E. Harari, L. Schmite, B. Troutman, and S. Wang, “A 256-bit nonvolatile static RAM,” in 1978 Int. Solid State Circuits Conf. Tech. Digest, pp. 108–109, Feb. 1978.
36. See, for example, Texas Instruments Data Sheet MOS LSI TMS2516JL and TMS2532JL 16K and 32K EPROMS, Apr. 1978.
37. H. R. Huff, R. Halvorson, T. L. Chiu, and D. Guterman, submitted to Fall 1978 Electrochemical Society Meet.
38. D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable FAMOS read-only memory,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 301–306, Oct. 1971.
39. J. J. Barnes, J. L. Linden, and J. R. Edwards, “Operation and characterization of n-channel EPROM cells,” in Int. Electron Devices Meet. Digest Tech. Papers, p. 173, Dec. 1976.
40. H. Shichman and D. A. Hodges, IEEE J. Solid-State Circuits, vol. SC-3, pp. 285–289, Sept. 1968.
41. F. F. Fang and A. B. Fowler, “Hot electron effects and saturation velocities in silicon inversion layers,” J. Appl. Phys., vol. 41, pp. 1825–1831, Mar. 1970.
42. H. Kroemer, “Hot-electron relaxation effects in devices,” Solid-State Electron., vol. 21, pp. 61–67, 1978.
43. T. H. Ning, “Hot-electron emission from silicon into silicon dioxide,” Solid-State Electron.,vol. 21, pp. 273–282,1978.
44. R. R. Troutman, “Silicon surface emission of hot electrons,” Solid-State Electron., vol. 21, pp. 283–289,1978.
45. S. M. Sze, Physics of Semiconductor Devices, New York: Wiley, 1969, ch. 6.
46. 2” J. Appl. Phys., vol. 45, pp. 5373–5378, Dec. 1974.
47. 2” Appl. Phys. Lett., vol. 26, pp. 248–250, Mar. 1975.
48. S. A. Abbas and C. A. Barile, “P-channel rewritable avalanche injection device (RAID) operation and degradation mechanisms,” in 13th Annu. Proc. Reliability Physics (Las Vegas, NV, vol. 13, 1976), pp. 1–5.
49. 2” J. Appl. Phys., vol. 40, pp. 278–283, Jan. 1969.
50. 2” Solid-State Electronics, vol. 20, pp. 11–18, 1977.
51. D. J. DiMaria and D. R. Kerr, “Interface effects and high conductivity in oxides grown from poly crystalline silicon,” Appl. Phys. Lett., vol. 27, pp. 505–507, Nov. 1975.
52. H. Iizuka, F. Masuoka, T. Sato, and M. Ishikawa, “Electrically alterable avalanche-injection-type MOS read-only memory with stacked-gate structure,” IEEE Trans. Electron Devices, vol. ED-23, pp. 379–387, Apr. 1976.
53. D. R. Kerr, “Mechanism of conduction in oxide growth on poly crystalline silicon,” Electrochemical Society Extended Abstracts (Oct. 1976), pp. 839–841.
54. R. A. Anderson and D. R. Kerr, “Evidence for surface asperity mechanism of conductivity in oxide grown on poly crystalline silicon,”J. Appl. Phys.,vol. 48, pp. 4834–4836, Nov. 1977.
55. T. I. Kamins and E. L. MacKenna, “Thermal oxidation of polycrystalline silicon films,” Metallurgical Trans., vol. 2, pp. 2244–2292, Aug. 1971.
56. D. K. Schroder and R. N. Thomas, “Experimental confirmation of the Fowler-Nordheim law for large-area field emitter ar:ays,” Appl. Phys. Lett., vol. 23, pp. 15–16, July 1973.
57. D. J. DiMaria, D. R. Young, and D. W. Ormond, “Use of electron-trapping region to reduce leakage currents and improve break-down characteristics of MOS structures,” Appl. Phys. Lett., vol. 31, pp. 680–682, Nov. 1977.
58. 2” J. Electrochem. SocSolid-State ScL Technovol. 123, pp. 42–47, Jan. 1976.
59. T. W. Hickmott, “Annealing of surface states in polycrystelline- silicon-gate capacitors,” J. Appl. Phys., vol. 48, pp.723–733 Feb. 1977.
60. 2” Appl. Phys. Lett., vol. 30, pp. 601–603, June 1977.
61. 2” J. Appl. Phys., vol. 49, pp. 2478–2489, Apr. 1978.
62. R. H. Walden, “A method for the determination of high,field conduction laws in insulating films in the presence of trapped charge,” J. Appl. Phys., vol. 43, pp. 1178–1186, Mar. 1972.
63. J. F. Verwey, “Nonvolatile semiconductor memories,” J.:com Advances in Electronics and Electron Physics, vol. 41, L. Mal ton, Ed. New York: Academic, 1976, p. 249.