The Anomalous Behavior of Flip-Flops in Synchronizer Circuits

IEEE Transactions on Computers

Volumn C-28, Issue 3, 1979, Pages 273-276

  Fleischhammer, Werner ^a   Dortok, Osman ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS - CIRCUITS;

ELECTRONIC CIRCUITS, FLIP FLOP;

EID: 0018445468     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1979.1675337     Document Type: Article

References (4)

1. I. Catt, “Time loss through gating of asynchronous logic signal pulses,” IEEE Trans. Electron. Comput. (Short Notes), vol. EC-15, pp. 108–111, Feb. 1966.
2. T. J. Chaney and C. E. Molnar, “Anomalous behavior of synchronizers and arbiter circuits,” IEEE Trans. Comput., vol. C-22, 421–422, Apr. 1973.
3. D. J. Kinniment and D. B. Edwards, “Circuit technology in a large computer system,” Radio Electron. Eng., vol. 43, pp. 435–441, July 1973.
4. W. Fleischhammer, G. Schneider, and G. Koppe, “T3L achieves C-MOS noise immunity while retaining TTL speed,” Electronics, vol. 47, pp. 94–97, Mar. 7, 1974.