BiMOS Micropower IC's

IEEE Journal of Solid-State Circuits

Volumn 13, Issue 6, 1978, Pages 791-798

  Schade, Otto H ^a  

^a FCA UNESP   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPOWER IC; SMOKE DETECTORS;

INTEGRATED CIRCUITS;

EID: 0018046045     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1978.1052052     Document Type: Article

References (14)

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2. O. H. Schade, Jr., “BiMOS micropower IC’s,” in ISSCC Dig. Tech. Papers, vol. XXI, Feb. 1978, p. 230.
3. —, “Advances in BiMOS integrated circuits,” RCA Rev., June 1978.
4. Y. Hayashi and Y. Tarui, Tech. Group on Semiconductors and Semiconductor Devices, IECE Japan, SSD-67-6, 1967.
5. P. Richman, “Theoretical threshold voltages for MOS field effect transistors,” Solid-State Electron., vol. 11, p. 869, 1968.
6. W. M. Gosney, “Subthreshold drain leakage current of MOS devices under surface depletion conditions,” IEEE Trans. Electron Devices, vol. ED-19, p. 213, Feb. 1972.
7. R. R. Troutman and S. N. Chakravarti, “Subthreshold characteristics of insulated-gate field-effect transistors,” IEEE Trans. Circuit Theory, vol. CT-20, p. 659, Nov. 1973.
8. E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, vol. SC-12, p. 224, June 1977.
9. J. Fellrath and E. Vittoz, “Small signal model of MOS transistors in weak inversion,” Ecole Polytechnique Federale De Lausanne, Journees d’Electronique, Session C4, 1977.
10. Y. P. Tsividis and R. W. Ulmer, “A CMOS reference voltage source,” in ISSCC Dig. Tech. Papers, vol. XXI, Feb. 1978, p. 48.
11. O. H. Schade, Jr., “A new generation of MOS/bipolar operational amplifiers,” RCA Rev., vol. 37, p. 404, Sept. 1976.
12. A. J. Leidich, “Linear monolithic circuit techniques,” paper 740012 in Automotive Electronics. New York: SAE, Feb. 1974, p. 67.
13. J. E. Solomon, “The monolithic op amp; A tutorial study,” IEEE J. Solid-State Circuits, vol. SC-9, Dec. 1974, pp. 314–332.
14. O. H. Schade, Jr., “Matching of semiconductor device characteristics,” U.S. Patent 3886435, issued Feb. 4, 1975.