Submicron Channel MOSFET's Logic Under Punchthrough

IEEE Journal of Solid-State Circuits

Volumn 13, Issue 5, 1978, Pages 572-577

  Nakamura, Tetsuo ^a   Yamamoto, Minoru ^a   Ishikawa, Hajime ^a   Shinoda, Masaichi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET;

TRANSISTORS, FIELD EFFECT;

EID: 0018026982     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1978.1051102     Document Type: Article

References (12)

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8. S. Muramoto, N. Miyahara, and Y. Sunohara, “Characteristics of MOS field effect transistor at punchthrough” (in Japanese), IECE Trans., vol. 58-C, pp. 501–508, Sept. 1975.
9. J. Nishizawa, T. Terasaki, and J. Shibata, “Field-effect transistor versus analog transistor (static induction transistor),” IEEE Trans. Electron Devices, vol. ED-22, pp. 185–197, Apr. 1975.
10. F. H. DeLa Moneda, “Threshold voltage from numerical solution of the two-dimensional MOS transistor,” IEEE Trans. Circuit Theory, vol. CT-20, pp. 666–673, Nov. 1973.
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