Theory and Breakdown Voltage for Planar Devices with a Single Field Limiting Ring

IEEE Transactions on Electron Devices

Volumn 24, Issue 2, 1977, Pages 107-113

  Adler, Michael S ^a   Temple, Victor A K ^a   Ferro, Armand P ^a   Rustay, R C ^a  

^a GENERAL ELECTRIC COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES;

EID: 0017455141     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1977.18688     Document Type: Article

References (12)

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3. M. S. Adler, in Technical Digest 1974 IEEE IEDM (Washington, DC, Dec. 10–12, 1974), pp. 255–259.
4. M. Bakowski and K. I. Lundstrom, IEEE Trans. Electron Devices, vol. ED-20, pp. 550–563, 1973.
5. V. A. K. Temple and M. S. Adler, IEEE Trans. Electron Devices, vol. ED-22, pp. 910–916, 1975.
6. P. E. Gray et al., Physical Electronics and Circuit Models of Transistors. SEEC Series vol., 2, New York: Wiley, 1964, p. 20.
7. M. S. Adler et al., Internal GE Report, “Theoretical basis for field calculations in multi-dimensional reverse biased semiconductor structures,” #75CRD149 (available by writing to the authors).
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9. J. Cornu, IEEE Trans. Electron Devices, vol. ED-20, pp. 347–352, 1973.
10. R. Van Overstraeten and H. DeMan, Solid-State Electron., vol. 13, pp. 583–608, 1970.
11. C. A. Lee et al., Phys. Rev., vol. 134, A761, 1964.
12. J. A. Moll and R. Van Overstraeten, Solid-State Electron., vol. 6, pp. 147–157, 1962.