Electrically Alterable Avalanche-Injection-Type MOS READ-ONLY Memory with Stacked-Gate Structure

IEEE Transactions on Electron Devices

Volumn 23, Issue 4, 1976, Pages 379-387

  Iizuka, Hisakazu Iizuka ^a   Masuoka, Fujio ^a   Sato, Tai ^a   Ishikawa, Mistuaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MIS; TRANSISTORS, FIELD EFFECT;

DATA STORAGE, SEMICONDUCTOR;

EID: 0016939689     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1976.18415     Document Type: Article

References (11)

1. D. Frohman-Bentchkowsky, “A fully-decoded 2048-bit electrically-programmable MOS-ROM,” in 1971 ISSCC Tech. Dig., pp. 80–81, Feb. 1971. See also “Memory behavior in a floating-gate avalanche-injection MOS (FAMOS) structure,” Appl. Phys. Lett., vol. 18. pp. 332–334, Aug. 1971.
2. H. Hara, T. Sato, Y. Takeishi, K. Ohuchi, H. Tango, H. Iizuka, Y. Yasuda, and F. Masuoka, “Avalanche-injection Mos read-only memory,” in Proc. 3rd Conf. Solid State Devices, (Tokyo, Japan), Aug. 1971. See also Suppl. J. Japan Soc. Appl. Phys., vol. 41. nn. 163–172. 1972.
3. H. Iizuka, T. Sato, F. Masuoka, K. Ohuchi, H. Hara, H. Tango, M. Ishikawa, and Y. Takeishi, “Stacked-gate avalanche-injection type MOS (SAMOS) memory,” in Proc. 4th Conf. Solid State Devices, (Tokyo, Japan), Aug. 1972; see also ibid, vol. 42, pp. 158–166, 1973 and H. Iizuka, T. Sato, F. Masuoka, K. Ohuchi, H. Hara, and Y. Takeishi, “A fully-decoded 2048-bit avalanche-injection type, electrically alterable ROM,” in 1972 IEDM, Washington. DC. Late News 7.6. Dec. 1972.
4. F. Masuoka, M. Ishikawa, T. Sato, and H. Iizuka, “An electrically programmable and erasable 2048-bit stacked-gate MOS ROM,” in 1973 IEDM, Washington, DC, Late News 7.8, Dec. 1973.
5. Y. Tarui, Y. Hayashi, and K. Nagai, “Proposal of electrically reprogrammable, nonvolatile semiconductor memory,” in Proc. 3rd Conf. Solid State Devices (Tokyo, Japan), Aug. 1971; Suppl. J. Japan Soc. Appl. Phys., vol. 41, pp. 155–162, 1973.
6. D. M. Brown, “The self-registered MOSFET-A brief review,” Solid-State Technol., 33–45, Apr. 1972.
7. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, pp. 278–283, 1969.
8. H. Hara, Y. Okamoto, and H. Ohnuma, “A new instability in MOS transistor caused by hot electron and hole injection from drain avalanche plasma into gate oxide,” Japan. J. Appl. Phys., vol. 9. PP. 1103–1112. Sent. 1970.
9. T. H. Distefano, “Barrier inhomogeneities on a Si-SiO 2 interface by scanning internal photoemission,” Appl. Phys. Lett., vol. 19, pp. 280–282, 1971.
10. E. H. Snow, “Fowler-Nordheim tunneling in SiO 2 films,” Solid State Commun., vol. 5, PP.813–815, Oct. 1967.
11. H. Nozawa, F. Masuoka, M. Ishikawa, and H. Iizuka, “Avalanche-Injection type MOS memory III. Retention,” in Preprint of the 35th Annu. Meet. Japan Society of Applied Physics (Fukui, Japan, 8a-Q-3), Oct. 1974.