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1
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33747020799
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The diagnosis of asynchronous sequential switching systems
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Aug.
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S. Seshu and D. N. Freeman “The diagnosis of asynchronous sequential switching systems,” IRE Trans. Electron. Comput., vol. EC-11, pp. 459–465, Aug. 1962.
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(1962)
IRE Trans. Electron. Comput.
, vol.EC-11
, pp. 459-465
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Seshu, S.1
Freeman, D.N.2
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2
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0014643344
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A three value computer design verification system
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J. S. Jephson, R. P. McQuarrie, and R. E. Vogelsberg “A three value computer design verification system,” IBM Syst. J., vol. 8, no. 3, pp. 178–188, 1969.
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(1969)
IBM Syst. J.
, vol.8
, Issue.3
, pp. 178-188
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Jephson, J.S.1
McQuarrie, R.P.2
Vogelsberg, R.E.3
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3
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84942006854
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Fairchild Semiconductor, Mountain View, Calif., Oct.
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FAIRSIM II User's Manual, Fairchild Semiconductor, Mountain View, Calif., Oct. 1969.
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(1969)
FAIRSIM II User's Manual
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4
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0014923407
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A model and implementation of a universal time delay simulator for large digital nets
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S. A. Szygenda, D. M. Rouse, and E. W. Thompson, “A model and implementation of a universal time delay simulator for large digital nets,” in 1970 Spring Joint Computer Conf., AFIPS Conf. Proc., pp. 207–216.
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1970 Spring Joint Computer Conf., AFIPS Conf. Proc.
, pp. 207-216
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Szygenda, S.A.1
Rouse, D.M.2
Thompson, E.W.3
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5
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85058889921
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TEGAS 2—Anatomy of a general purpose test generation and simulation system for digital logic
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(June)
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S. A. Szygenda, “TEGAS 2—Anatomy of a general purpose test generation and simulation system for digital logic,” in Proc. 9th ACM-IEEE Design Automation Workshop (June 1972), pp. 116–127.
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(1972)
Proc. 9th ACM-IEEE Design Automation Workshop
, pp. 116-127
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Szygenda, S.A.1
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6
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85050924325
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The concurrent simulation of nearly identical digital networks
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(Portland. Oreg., June)
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E. G. Ulrich and T. Baker, “The concurrent simulation of nearly identical digital networks,” in Proc. 10th ACM-IEEE Design Automation Workshop (Portland. Oreg., June 1973). pp. 145–150.
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(1973)
Proc. 10th ACM-IEEE Design Automation Workshop
, pp. 145-150
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Ulrich, E.G.1
Baker, T.2
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7
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84942008107
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GAZELLE—An interactive graphic logic design system
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presented at the ACM Nat. Conf., Atlanta, Ga., Aug., also ACM, SIGDA Newsletter, vol. 4, June 1974
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W. H. Sass, “GAZELLE—An interactive graphic logic design system,” presented at the ACM Nat. Conf., Atlanta, Ga., Aug. 1973; also ACM, SIGDA Newsletter, vol. 4, June 1974.
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(1973)
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Sass, W.H.1
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8
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84942008325
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A minicomputer-based logic fault simulator
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(Denver, Colo., June); also ACM, SIGDA Newsletter, vol. 4, Sept. 1974
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M. Flomenhoft and B. M. Csencsits, “A minicomputer-based logic fault simulator,” in Proc. 11th ACM-IEEE Design Automation Workshop (Denver, Colo., June 1974); also ACM, SIGDA Newsletter, vol. 4, Sept. 1974.
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(1974)
Proc. 11th ACM-IEEE Design Automation Workshop
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Flomenhoft, M.1
Csencsits, B.M.2
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9
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0016114316
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LAMP: Logic circuit simulators
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Oct.
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S. G. Chappell, C. H. Elmendorf, and L. D. Schmidt “LAMP: Logic circuit simulators,” Bell Syst. Tech. J., vol. 53, pp. 1451–1476, Oct. 1974.
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(1974)
Bell Syst. Tech. J.
, vol.53
, pp. 1451-1476
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Chappell, S.G.1
Elmendorf, C.H.2
Schmidt, L.D.3
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10
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0016114334
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LAMP: System description
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Oct.
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H. Y. Chang, G. W. Smith, Jr., and R. B. Walford “LAMP: System description,” Bell Syst. Tech. J., vol. 53, pp. 1431–1449, Oct. 1974.
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(1974)
Bell Syst. Tech. J.
, vol.53
, pp. 1431-1449
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Chang, H.Y.1
Smith, G.W.2
Walford, R.B.3
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11
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84942007069
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Operational features of an MOS timing simulator
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to be publish
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P. Kozak, H. K. Gummel, and B. R. Chawla, “Operational features of an MOS timing simulator,” to be published.
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-
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Kozak, P.1
Gummel, H.K.2
Chawla, B.R.3
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12
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84942008058
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Development of a compact process-oriented dc model for short channel IGFETs
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presented at the 8th Asilomar Conf. Circuits, Systems and Computers, Pacific Grove, Calif., Dec.
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H. C. Poon, “Development of a compact process-oriented dc model for short channel IGFETs,” presented at the 8th Asilomar Conf. Circuits, Systems and Computers, Pacific Grove, Calif., Dec. 1974.
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(1974)
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Poon, H.C.1
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13
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85051627160
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Computer-aided prediction of delays in LSI logic systems
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(Portland, Oreg., June)
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D. J. Pilling and H. B. Sun, “Computer-aided prediction of delays in LSI logic systems,” in Proc. 10th ACM-IEEE Design Automation Workshop (Portland, Oreg., June 1973), pp. 182–186.
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(1973)
Proc. 10th ACM-IEEE Design Automation Workshop
, pp. 182-186
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Pilling, D.J.1
Sun, H.B.2
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14
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84942009147
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An MOS circuit simulator for integrated circuit design
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(Boston, Mass., Apr.)
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B. R. Chawla, H. K. Gummel, and P. Kozak, “An MOS circuit simulator for integrated circuit design,” in Proc. 1975 IEEE Int. Symp. Circuits and Systems (Boston, Mass., Apr. 1975).
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(1975)
Proc. 1975 IEEE Int. Symp. Circuits and Systems
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Chawla, B.R.1
Gummel, H.K.2
Kozak, P.3
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