On the Analysis of Fault Trees

IEEE Transactions on Reliability

Volumn R-24, Issue 3, 1975, Pages 175-185

  Bennetts, R G ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TREES;

RELIABILITY THEORY;

LOGIC CIRCUITS;

EID: 0016539257     PISSN: 00189529     EISSN: 15581721     Source Type: Journal    
DOI: 10.1109/TR.1975.5215143     Document Type: Article

References (9)

1. J.B. Fussell, G.J. Powers and R.G. Bennetts “Fault Trees-A State- of-the-Art Discussion,” IEEE Trans. Reliability, Vol. R-23, pp. 51- 55, April 1974.
2. R.G. Bennetts “Computer aided generation of test sequences for logical systems,” Ph.D. dissertation, University of Southhampton, 1972. (Not readily available).
3. R.G. Bennetts “A realistic approach to detection test set generation for combinational logic circuits,” BCS Computer Journal, Vol. 15, pp. 238-246, Aug. 1972.
4. J.B. Fussell “Fault tree analysis-concepts and techniques,” Proc. NATO Advanced Study Institute on Generic Techniques of System Reliability Assessment, Liverpool, July 1973. To be published by the Nordhoff Publishing Company.
5. R.B. Hurley “Probability maps,” IEEE Trans. Reliability, Vol. R-12, pp. 39-44, Sept. 1963.
6. E. Phibbs and S.H. Kuwamoto “Fault-tree analysis,” IEEE Trans. Reliability, Vol. R-23, p. 226, Oct. 1974. (Correspondence).
7. E. Phibbs and S.H. Kuwamoto “An efficient map method for processing multistate logic trees,” IEEE Trans. Reliability, Vol. R-21, pp. 93-98, May 1972.
8. L. Fratta and U.G. Montanari “A Boolean algebra method for computing the terminal reliability in a communication channel,” IEEE Trans. Circuit Theory, Vol. CT-20, pp. 203-211, May 1973.
9. M.A. Breuer “Heuristic switching expression simplification,” Proc. 1968 ACM National Conference, pp. 241-250, 1968. Dr. R.G. Bennetts//Department of Electronics//The University// Southampton S09 5NH ENGLAND