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Volumn C-24, Issue 1, 1975, Pages 62-71

The Boolean Difference and Multiple Fault Analysis

Author keywords

Boolean difference; combinational logic circuits; complete test set; minimal test set; multiple fault analysis

Indexed keywords

FAULT DIAGNOSIS;

EID: 0016439298     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1975.224083     Document Type: Article
Times cited : (35)

References (9)
  • 1
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    • (1959) SIAM J. Appl. Math. , vol.7 , pp. 487-498
    • Akers, S.B.1
  • 2
    • 0039607679 scopus 로고
    • Analyzing errors with the Boolean difference
    • July
    • F. F. Sellers, M. Y. Hsiao, and L. W. Bearnson “Analyzing errors with the Boolean difference,” IEEE Trans. Comput., vol. C-17, pp. 676–683, July 1968.
    • (1968) IEEE Trans. Comput. , vol.C-17 , pp. 676-683
    • Sellers, F.F.1    Hsiao, M.Y.2    Bearnson, L.W.3
  • 3
    • 0014616326 scopus 로고
    • A programmed fault detection algorithm for combinational switching networks
    • G. R. Smith and S. S. Yau, “A programmed fault detection algorithm for combinational switching networks,” in Proc. Nat. Electron. Conf., vol. 25, 1969, pp. 668–673.
    • (1969) Proc. Nat. Electron. Conf. , vol.25 , pp. 668-673
    • Smith, G.R.1    Yau, S.S.2
  • 4
    • 0015161219 scopus 로고
    • An efficient algorithm for generating complete test sets for combinational logic circuits
    • Nov.
    • S. S. Yau and Y.-S. Tang “An efficient algorithm for generating complete test sets for combinational logic circuits,” IEEE Trans. Comput., vol. C-20, pp. 1245–1251, Nov. 1971.
    • (1971) IEEE Trans. Comput. , vol.C-20 , pp. 1245-1251
    • Yau, S.S.1    Tang, Y.-S.2
  • 5
    • 0015299663 scopus 로고
    • Path sensitization, partial Boolean difference, and automated fault diagnosis
    • Feb.
    • A. C. L. Chiang, I. S. Reed, and A. V. Banes “Path sensitization, partial Boolean difference, and automated fault diagnosis,” IEEE Trans. Comput., vol. C-21, pp. 189–195, Feb. 1972.
    • (1972) IEEE Trans. Comput. , vol.C-21 , pp. 189-195
    • Chiang, A.C.L.1    Reed, I.S.2    Banes, A.V.3
  • 6
    • 0015160788 scopus 로고
    • On the design of multiple fault diagnosable network
    • Nov.
    • D. R. Schertz and G. Metze “On the design of multiple fault diagnosable network,” IEEE Trans. Comput., vol. C-20, pp. 1361–1364, Nov. 1971.
    • (1971) IEEE Trans. Comput. , vol.C-20 , pp. 1361-1364
    • Schertz, D.R.1    Metze, G.2
  • 7
    • 84947657064 scopus 로고
    • Near-minimal fault analysis in combinational logic circuits
    • Ph.D. dissertation, Dep. Elec. Eng., Univ. of Pittsburgh, Pittsburgh, Pa
    • C. T. Ku, “Near-minimal fault analysis in combinational logic circuits,” Ph.D. dissertation, Dep. Elec. Eng., Univ. of Pittsburgh, Pittsburgh, Pa., 1973.
    • (1973)
    • Ku, C.T.1
  • 8
    • 0015284302 scopus 로고
    • Multiple fault detection in combinational networks
    • Jan.
    • J. W. Gault, J. P. Robinson, and S. M. Reddy “Multiple fault detection in combinational networks,” IEEE Trans. Comput., vol. C-21, pp. 31–36, Jan. 1972.
    • (1972) IEEE Trans. Comput. , vol.C-21 , pp. 31-36
    • Gault, J.W.1    Robinson, J.P.2    Reddy, S.M.3
  • 9
    • 1842421475 scopus 로고
    • Boolean difference calculus and fault finding
    • Jan.
    • I. S. Reed “Boolean difference calculus and fault finding,” SIAM J. Appl. Math., vol. 24, pp. 134–143, Jan. 1973.
    • (1973) SIAM J. Appl. Math. , vol.24 , pp. 134-143
    • Reed, I.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.