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Volumn C-24, Issue 1, 1975, Pages 72-79

Synthesis Algorithms for 2-level MOS Networks

Author keywords

Boolean expression; MOS complex cell; negative function; optimal 2 level network; true vector

Indexed keywords

INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICES, MIS;

EID: 0016433897     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1975.224084     Document Type: Article
Times cited : (20)

References (11)
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    • (Short Notes), June
    • T. Ibaraki, “Gate interconnection minimization of switching networks using negative gates,” IEEE Trans. Comput. (Short Notes), vol. C-20, pp. 698–706, June 1971.
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    • Ibaraki, T.1
  • 5
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    • Synthesis of logic networks with MOS complex cells
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  • 8
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    • Memo, Bell Telephone Laboratories
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  • 9
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    • Minimal negative gate networks
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    • K. Nakamura, N. Tokura, and T. Kasami “Minimal negative gate networks,” IEEE Trans. Comput., vol. C-21, pp. 5–11, Jan. 1972.
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  • 10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.