Anomalous Behavior of Synchronizer and Arbiter Circuits

IEEE Transactions on Computers

Volumn C-22, Issue 4, 1973, Pages 421-422

  Chaney, Thomas J ^a   Molnar, Charles E ^a  

^a WASHINGTON UNIVERSITY   (United States)

Author keywords

Asynchronous interactions; binary switching time; flip flop metastable region; interrupt failure; synchronizer failure mode

Indexed keywords

ELECTRONIC CIRCUITS, FLIP FLOP;

SWITCHING THEORY;

EID: 0015605213     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1973.223730     Document Type: Article

References (6)

1. W. H. Ware, Digital Computer Technology and Design, vol. II. New York: Wiley, 1963, p. 13.18.
2. H. J. Gray, Digital Computer Engineering. Englewood Cliffs, N.J.: Prentice-Hall, 1963, pp. 198–201.
3. I. Catt, “Time loss through gating of asynchronous logic signal pulses,” IEEE Trans. Electron. Comput. (Short Notes), vol. EC-15, pp. 108–111, Feb. 1966.
4. W. M. Littlefield and T. J. Chaney, “The glitch phenomenon,” Comput. Syst. Lab., Washington Univ., St. Louis, Mo., Tech. Memo. 10, Dec. 1966.
5. G. R. Couranz, “An analysis of binary circuits under marginal triggering conditions,” Comput. Syst. Lab., Washington Univ., St. Louis, Mo., Tech. Rep. 15, Nov. 1969.
6. T. J. Chaney, S. M. Ornstein, and W. M. Littlefield, “Beware the synchronizer,” presented at the COMPCON-72 IEEE Comput. Soc. Conf., San Francisco, Calif., Sept. 12–14, 1972.