Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells

IEEE Journal of Solid-State Circuits

Volumn 7, Issue 5, 1972, Pages 336-340

  Stein, Karl U ^a   Sihling, Aarne ^a   Doering, Elko ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR;

EID: 0015416220     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1972.1052889     Document Type: Article

References (10)

1. D. Lund, G. A. Allen, S. R. Andersen, and G. K. Tu, “Design of a megabit semiconductor memory system,” in Proc. AFIPS Fall Joint Computer Conf., pp. 53–62, Dec. 1970.
2. W. M. Regitz and J. Karp, “A three-transistor cell, 1024-bit, 600 ns MOS RAM,” ISSCC Dig. Tech. Papers, pp. 42–43, Feb. 1970.
3. W. M. Regitz and J. Karp, “Fully decoded random-access 1024-bit dynamic memory 1103,” Intel Corp., Mountain View, Calif., data sheet, Oct. 1970.
4. J. A. Karp, W. M. Regitz, and S. Chou, “A 4096-bit dynamic MOS RAM,” ISSCC Dig. Tech. Papers, pp. 10–11, Feb. 1972.
5. L. M. Terman, “MOSFBT memory circuits,” Proc. IEEE, vol. 59, pp. 1044–1058, July 1971.
6. R. H. Dennard, “Field-effect transistor memory,” U. S. Patent 3 387 286, June 4, 1968.
7. J. O. Paivinen, R. B. Rubinstein, L. Cohen, and L. T. Baker, “Read-write random-access memory system having single device memory cells,” U. S. Ser. 809 223, Mar. 21, 1969.
8. L. Cohen, R. Green, K. Smith, and J. L. Seely, “Single-transistor cell makes room for more memory on a MOS chip,” Electronics, p. 69, Aug. 2, 1971.
9. W. S. Boyle and G. E. Smith, “Charge-coupled semiconductor devices,” Bell Syst. Tech. J. (Briefs), pp. 587–593, Apr. 1970.
10. A. S. Grove and D. J. Fitzgerald, “Surface effects on p-n junction-characteristics of surface space-charge regions under nonequilibrium conditions,” Solid-State Electron., vol. 9, p. 783, Sept. 1966.