A NAND Model for Fault Diagnosis in Combinational Logic Networks

IEEE Transactions on Computers

Volumn C-20, Issue 12, 1971, Pages 1496-1506

  Hayes, John P ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Combinational networks; fault diagnosis; fault masking; indistinguishable faults; multiple fault detection; NAND networks

Indexed keywords

COMPUTERS, DIGITAL, LOGIC DESIGN;

FAULT DIAGNOSIS; NAND NETWORKS;

COMPUTERS, DIGITAL--CIRCUITS;

EID: 0015198646     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1971.223162     Document Type: Article

References (13)

1. [1] H. Y. Chang, E. C. Manning, and G. Metze, Fault Diagnosis of Digital Systems. New York: Wiley, 1970.
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3. D. R. Schertz, “On the representation of digital faults,” Coordinated Science Lab., Univ. Illinois, Urbana, Rep. R-418, May 1969.
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10. J. P. Hayes, “A study of digital network structure and its relation to fault diagnosis,” Coordinated Science Lab., Univ. Illinois, Urbana, Rep. R-467, May 1970.
11. E. S. Davidson, “An algorithm for NAND decomposition under network constraints,” IEEE Trans. Comput., vol. C-18, Dec. 1969, pp. 1098–1109.
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13. J. P. Roth, W. G. Bouricius, and P. R. Schneider, “Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,” IEEE Trans. Electron. Comput., vol. EC-16, Oct. 1967, pp. 567–580.