A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits

IEEE Transactions on Computers

Volumn C-20, Issue 11, 1971, Pages 1364-1370

  Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Digital logic simulation; fault detection test generation; random test generation; S algorithm; sequential circuits; three valued simulation

Indexed keywords

COMPUTERS, DIGITAL, SIMULATION;

FAULT DETECTION; SEQUENTIAL CIRCUITS;

LOGIC CIRCUITS;

EID: 0015161126     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1971.223140     Document Type: Article

References (5)

1. J.P., Roth, W.G., Bouricius, P.R., Schneider, Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits, IEEE Trans. Electron. Comput., EC-16, 567, 580, Oct. 1967
2. M.A., Breuer, Functional partitioning and simulation of digital circuits, IEEE Trans. Comput., EC-19, 1038, 1046, Nov. 1970
3. S., Seshu, D.N., Freeman, The diagnosis of asynchronous sequential switching systems, IRE Trans. Electron. Comput., EC-11, 459, 465, Aug. 1962
4. J.S., Jephson, R.P., McQuarrie, R.E., Vogelsberg, A three-value computer design verification system, IBM Syst. J., 178, 188 1969
5. E.B., Eichelberger, Hazard detection in combinational and sequential switching circuits, IBM J. Res. Develop, 90, 99, Mar. 1965