Failure-Tolerant Sequential Machines with Past Information

IEEE Transactions on Computers

Volumn C-20, Issue 4, 1971, Pages 392-396

  Tohma, Yoshihiro ^a   Aoyagi, Susumu ^a,b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Error correction capability; machine; reliability; sequential; state assignment

Indexed keywords

RELIABILITY;

SEQUENTIAL MACHINES; STATE ASSIGNMENT;

AUTOMATA THEORY;

EID: 0015050317     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1971.223254     Document Type: Article

References (8)

1. W. W. Peterson, Error Correcting Codes. Cambridge, Mass.: M.I.T. Press, 1961.
2. D. B. Armstrong, “A general method of applying error correction to synchronous digital systems,” Bell Sys. Tech. J., vol. 40, Mar. 1961, pp. 577–593.
3. R. L. Russo, “Synthesis of error-tolerant counters using minimum distance three state assignment,” IEEE Trans. Electronic Computers, vol. EC-14, June 1965, pp. 359–366.
4. W. H. Pierce, Failure Tolerant Computer Design. New York: Academic Press, Inc., 1965.
5. W. Kammerer, “Zur Konstruktion selbstkorrigierender Automata,” Elektronische Informationsverarbertung und Kybernetik, vol. 2, 1966, pp. 165–175.
6. J. Beister, “On the implementation of failure-tolerant counters,” IEEE Trans. Computers (Short Notes), vol. C-17, Sept. 1968, pp. 885– 886.
7. M. Phister, Logical Design of Digital Digital Computers. New York: Wiley, 1958.
8. G. A. Korn and T. M. Korn, Mathematical Handbook for Scientist and Engineers, vol. 13. New York: McGraw-Hill, 1961, pp. 4–7.