Synthesis of Networks with a Minimum Number of Negative Gates

IEEE Transactions on Computers

Volumn C-20, Issue 1, 1971, Pages 49-58

  Ibaraki, Toshihide ^a   Muroga, Saburo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Conjoint; logical design; minimal cover; MOS; negative gates; network with minimum number of gates; supplementary columns; truth table

Indexed keywords

COMPUTERS, DIGITAL; INTEGRATED CIRCUITS; ITCOB; LOGIC CIRCUITS; LOGIC DESIGN;

EID: 0014980091     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1971.223081     Document Type: Article

References (9)

1. S.B. Akers, “A truth table method for the synthesis of combinational logic,” IRE Trans. Electronic Computers, vol. EC-10, pp. 604–615, December 1961.
2. “Synthesis of combinational logic using three-input majority gates,” Proc. 3rd Ann. Symp. on Switching Circuit Theory and Logical Design, pp. 150–157, October 1962.
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4. T. Ibaraki and S. Muroga, “Minimization of switching networks using negative functions,” Department of Computer Science, University of Illinois, Urbana, Ill., Rept. 309, February 1969.
5. T. Ibaraki, “Minimization of switching networks of negative gates (2)“(in Japanese), Automaton Group, Inst. Elec. Commun. Japan, Paper A69–67, January 1970.
6. S. Muroga, Threshold Logic, Lecture note, Department of Computer Science, University of Illinois, Urbana, Ill., 1967–1968; also New York: Wiley, to be published in 1971.
7. K. Nakamura, N. Tokura, and T. Kasami, “Decomposition of logical functions into monotone functions,” (in Japanese), Automaton Group, Inst. Elec. Commun. Japan, Paper A69–66, January 1970.
8. R.F. Spencer, “MOS complex gates in digital systems design,” IEEE Computer Group News, vol. 2, pp. 47–56, September 1969.
9. E. Thomas and J.D. Callan, “Slow, but small, may win the race,” Electronics, vol. 40, pp. 179–182, February 20, 1967.