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Volumn , Issue , 2002, Pages 70-77

A flexible architecture for H.263 video coding

Author keywords

Cameras; Data preprocessing; Discrete cosine transforms; Motion compensation; Motion control; Motion estimation; Process control; Processor scheduling; Reduced instruction set computing; Video coding

Indexed keywords

CAMERAS; COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; IMAGE CODING; MICROPROCESSOR CHIPS; MOTION ANALYSIS; MOTION COMPENSATION; MOTION CONTROL; MOTION ESTIMATION; PROCESS CONTROL; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; SYSTEMS ANALYSIS; VIDEO SIGNAL PROCESSING;

EID: 0013145684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2002.1115353     Document Type: Conference Paper
Times cited : (1)

References (20)
  • 4
    • 0019543368 scopus 로고
    • Image data compression: A review
    • 3. March
    • A. K. lain. "Image Data Compression: A Review". Proceedings of the IEEE, vo169, n° 3. March 1981.
    • (1981) Proceedings of the IEEE , vol.69
    • Lain, A.K.1
  • 5
    • 0035423153 scopus 로고    scopus 로고
    • Optimization of H.263 video encoding using a single processor computer: Performance tradeoffs and benchmarking
    • 8. Aug.
    • S. M. Akramullah, I. Ahmad and M. L. Liou. "Optimization of H.263 Video Encoding Using a Single Processor Computer: Performance Tradeoffs and Benchmarking". IEEE Transactions on Circuits and Systemsfor Video Technology, vol. 11, n° 8. Aug. 2001.
    • (2001) IEEE Transactions on Circuits and Systemsfor Video Technology , vol.11
    • Akramullah, S.M.1    Ahmad, I.2    Liou, M.L.3
  • 8
    • 0033221281 scopus 로고    scopus 로고
    • A Single Chip CIF 30-Hz, H261, H263 and H263+ video encoder/decoder with embedded display controller
    • M. Harrand, J. Sanches, A. Bellon, J. Bulone, A. Tournier. "A Single Chip CIF 30-Hz, H261, H263 and H263+ video encoder/decoder with embedded display controller". IEEE Journal ofSolid-State Circuits, Vol.: 34 Issue: 11. 1999. Pag: 1627-1633.
    • (1999) IEEE Journal OfSolid-State Circuits , vol.34 , Issue.11 , pp. 1627-1633
    • Harrand, M.1    Sanches, J.2    Bellon, A.3    Bulone, J.4    Tournier, A.5
  • 12
    • 0030415090 scopus 로고    scopus 로고
    • A high-perfonnance architecture with a macroblock-level-pipeline for MPEG-2 coding
    • J. M. Fernandez, F. Moreno, J. Meneses. "A High-Perfonnance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding". Real Time Imaging Journal, Vo12, 1996. Pags 331-340.
    • (1996) Real Time Imaging Journal , vol.2 , pp. 331-340
    • Fernandez, J.M.1    Moreno, F.2    Meneses, J.3
  • 13
    • 0013056118 scopus 로고    scopus 로고
    • VLSI architecture for motion estimation using the three-step block matching algorithm
    • Designer Track
    • C. Sanz, M. Garrido, J. Meneses. "VLSI Architecture for Motion Estimation using the Three-Step Block Matching Algorithm". Design Automation and Test in Europe Conference, 1998. Designer Track. Pags. 45-50.
    • (1998) Design Automation and Test in Europe Conference , pp. 45-50
    • Sanz, C.1    Garrido, M.2    Meneses, J.3
  • 14
    • 0345339682 scopus 로고    scopus 로고
    • Low cost ASIC implementation of a three-step search block-matching algorithm for motion estimation in image coding
    • User's Forum Paper awarded with the "Best ASIC Prize
    • C. Sanz, M. A. Freire, J. Meneses. "Low Cost ASIC Implementation of a Three-Step Search Block-Matching Algorithm for Motion Estimation in Image Coding". Design Automation and Test in Europe Conference, 1999. User's Forum. Pags. 75-79. Paper awarded with the "Best ASIC Prize ".
    • (1999) Design Automation and Test in Europe Conference , pp. 75-79
    • Sanz, C.1    Freire, M.A.2    Meneses, J.3
  • 20
    • 84949638439 scopus 로고    scopus 로고
    • Fraunhofer-Gesellschaft-lIS
    • ClipPlayer V 1.1 b2. 1996 Fraunhofer-Gesellschaft-lIS.
    • (1996) ClipPlayer v 1.1 b2.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.