Monolithic 1.25Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages

  Wu, L ^a   Chen, H ^a   Nagavarapu, S ^a   Geiger, R ^a   Lee, E ^a   Black, W ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FREQUENCY CONTROL; ELECTRIC NETWORK TOPOLOGY; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

CHARGE PUMP; FIBRE CHANNEL TRANSCEIVER;

CMOS INTEGRATED CIRCUITS;

EID: 0012745224     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (3)