Annealing behavior of deep trap level in p-GaTe

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 37, Issue 6 A, 1998, Pages 3282-3283

  Shigetomi, Shigeru ^a   Ikari, Tetsuo ^b   Nakashima, Hiroshi ^c  

^a KURUME UNIVERSITY   (Japan)

^b UNIVERSITY OF MIYAZAKI   (Japan)

^c KYUSHU UNIVERSITY   (Japan)

Author keywords

Annealing; Deep level; GaTe; Layer semiconductor; Trap concentration

Indexed keywords

EID: 0012633966     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.37.3282     Document Type: Article

References (8)

1. C. Tatsuyama, Y. Watanabe and C. Hamaguchi: J. Phys. Soc. Jpn. 29 (1970) 150.
2. Yu. F. Andronov and Yu. F. Solomonov: Sov. J. Quantum Electron 18 (1988) 505.
3. G. Fischer and J. L. Brebner: J. Phys. Chem. Solids 23 (1962) 1363.
4. D. V. Lang: J. Appl. Phys. 45 (1974) 3014.
5. S. M. Sze: Physics of Semiconductor Devices (John Wiley & Sons, New York, 1969) p. 372.
6. D. V. Lang: J. Appl. Phys. 45 (1974) 3023.
7. H. Nakashima and K. Hashimoto: Jpn. J. Appl. Phys. 28 (1989) 1402.
8. A. Segura, K. Wünstel and A. Chevy: Appl. Phys. A 31 (1983) 139.