Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 1991-November, Issue , 1991, Pages 67-80

  Hammond, Jim ^a   Sery, George ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; DESIGN FOR TESTABILITY; ELECTRIC INSULATION TESTING; FAULT TOLERANCE; KNOWLEDGE BASED SYSTEMS; PROGRAM DEBUGGING; PROGRAM PROCESSORS; REVERSE ENGINEERING; VLSI CIRCUITS;

ELECTRICAL MONITORS; ELECTRICAL TESTS; FLASH TECHNOLOGY; I-V MEASUREMENTS; PROCESS DEVELOPMENT; PROCESS IMPROVEMENT; PRODUCTION YIELD; VERY LARGE ARRAYS;

DEFECTS;

EID: 0011889719     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1991.199947     Document Type: Conference Paper

References (12)

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3. H. Gaw et al, "A lOOnS 256K CMOS EPROM", IEEE ISSCC, 1985, pp 164-165.
4. R. Pashley and S. Lai, "Flash Memories: The Best of Two Worlds", IEEE Spectrum, Dec. 1989, pp 30-33.
5. J. Acken and M. Horowitz, "A Static RAM as a Fault Model Evaluator", IEEE Custom Int. Circ. Conf., 1987, pp 590-593.
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7. J. Hammond, B. Boerman, F. Voltmer, "Process Development and Circuit Design Interactions in VLSI Yield Improvement", Defect and Fault Tolerance in VLSI Systems, Vol 1, Ed. I. Koren, Plenum, 105 (1989).
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9. E. Sicard and K. Kinoshita, "On the Evaluation of Process-Fault Tolerance Ability of CMOS Integrated Circuits", Proc ITC 1990, pp 948-954.
10. H. Walker, "Yield Simulation for Integrated Circuits", Kluwer Academic Publishers, Boston, MA, 1987.
11. W. Maly and P. Nigh, "Built-in Current Testing - Feasibility Study", accepted to IEEE Trans on CAD.
12. H. Iizuka, F. Masuoka, T. Sato, M. Ishikawa, "Electrically Alterable Avalanche-Injection-Type MOS Read-Only Memory with Stacked-Gate Structures", IEEE Trans. Elect. Dev., ED-23, 379 (1976).