Electrochemical planarization of ULSI copper

Solid State Technology

Volumn 40, Issue 6, 1997, Pages 155-164

  Contolini, Robert J ^a,b,c   Mayer, Steven T ^a,d,e   Graff, Robert T ^a   Tarte, Lisa ^a   Bernhardt, Anthony F ^a,f  

^a LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

^b OHIO STATE UNIVERSITY   (United States)

^c Novellus Systems   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e PolyStor Corp   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER PLATING; COST EFFECTIVENESS; ELECTROLYTIC POLISHING; ELECTROPLATING; ULSI CIRCUITS; ELECTROCHEMISTRY; INTEGRATED CIRCUIT MANUFACTURE;

ANODIC ELECTROPOLISHING; CATHODIC PLATING; ELECTROCHEMICAL PLANARIZATION;

INTEGRATED CIRCUIT MANUFACTURE; COPPER PLATING;

EID: 0011498991     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (12)

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2. Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, p. 98, 1994.
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11. S. Mayer, et al., to be published.
12. S. Mayer, R. Contolini, A. Bernhardt, "Method and Apparatus for Spatially Uniform Electropolishing and Electrolytic Etching," US Patent #5,096,550, 1992.