Optimization of wire loop height for a cavity down plastic pin grid array package

Journal of Electronic Packaging, Transactions of the ASME

Volumn 120, Issue 2, 1998, Pages 194-200

  Chaudhry, I ^a   Barez, F ^a,b  

^a SAN JOSE STATE UNIVERSITY   (United States)

^b ASAT Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; OPTIMIZATION; THERMAL CYCLING; THERMAL EFFECTS;

PLASTIC PIN GRID ARRAY (PPGA) PACKAGES; WIRE LOOP HEIGHT;

ELECTRONICS PACKAGING;

EID: 0010602062     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2792620     Document Type: Article

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