An approach for power minimization using transformations

Workshop on VLSI Signal Processing 1992

Volumn , Issue , 1992, Pages 41-50

  Chandrakasan, Anantha ^a   Potkonjak, Miodrag ^b   Rabaey, Jan ^a   Brodersen, Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIR FILTERS; IIR FILTERS; VLSI CIRCUITS;

CMOS CIRCUITS; MAGNITUDE REDUCTION; ORDER DELAYS; POWER MINIMIZATION; REDUNDANCY ELIMINATION; SECOND ORDER VOLTERRA FILTER; SYSTEM THROUGHPUT;

SIGNAL PROCESSING;

EID: 0010177493     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISP.1992.639171     Document Type: Conference Paper

References (10)

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6. R. W. Brodersen, (ed.), "Anatomy of a Silicon Compiler", Klewer Academic Publishers, 1992.
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