SOURCE-LEVALLOOP OPTIMIZATIONFOR DSP CODE GENERATION

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 1999, Pages 2155-2158

  Su, Bogong ^a   Wang, Jian ^b   Esguerra, Andrew ^a  

^a WILLIAM PATERSON UNIVERSITY   (United States)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; PROGRAM COMPILERS;

'CURRENT; ASSEMBLY CODE; C COMPILERS; C++ CODES; CODEGENERATION; LOOP OPTIMIZATIONS; PERFORMANCE; SOFTWARE PIPELINING; SOURCE LEVEL;

C (PROGRAMMING LANGUAGE);

EID: 0010113808     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1999.758361     Document Type: Conference Paper

References (9)

1. A. Davis, “Tips for Writing More Efficient DSP C Code”, EDN, June 5, 1997,p.98.
2. T. Dillon, “The Use of Software Pipelining in Developing DSP Algorithms for the TMS320C6x”, Proc. of ICSPA797, Sept. 1997, 834-837.
3. P. Faraboschi,G. Desoli, and J. Fisher, ‘The Latest Word in Digital and Media Processing”,IEEE Signal Processing, vol. 15, No. 2, March 1998, 59-85.
4. M. Levy, “C Compilers for DSPs - Flex Their Muscles”, EDN, June 5, 1997,93-107
5. P. Marwedel, “Code Generation for Core Processors”, Proc. of DAC-97, 1997,232-237.
6. B. Rau and J. Fisher, “Instruction-level Parallel Processing: History, Overview, and Perspective”, The Journal of Supercomputing, 7(l), Jan. 1993.
7. B. Su et al, “URPR - an Extension of URCR for Software Pipelining”, Proc. of MICRO-19, 1986, 104-108.
8. B. Su et al, “A Study of Source-level Loop Optimization for DSP Code Generation”,Technical Report, College of Science and Health, William Paterson University, Aug. 1998.
9. J. Wang and B. Su, “Software Pipelining of Nested Loops for Real-time DSP Applications”, Proc. of ICASSP98, May, 1998.