Power factor correction using interleaving technique for critical mode switching converters

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn 1, Issue , 1998, Pages 905-910

  Ishii, Takuya ^a   Mizutani, Takuya ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL MODES; INTERLEAVED BOOST; INTERLEAVING TECHNIQUE; POWER FACTOR CORRECTION CONVERTERS; POWER FACTOR CORRECTIONS;

ELECTRIC POWER FACTOR; POWER ELECTRONICS; SWITCHING CIRCUITS;

POWER CONVERTERS;

EID: 0009681141     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PESC.1998.702007     Document Type: Conference Paper

References (3)

1. W. E. Rippel, "Optimizing Boost Chopper Charger Design", Solid-State Power Conversion Conference Proceedings, pp. Dl-1-Dl-20, 1979
2. B. A. Miwa, D. M. Otten. M. F. Schlecht, "High Efficiency Power Factor Correction using Interleaving Techniques", APEC 1992, pp. 557-568
3. Michael S. Elmore, "Input Current Ripple Cancellation in Synchronized, Parallel Connected Critically Continuous Boost Converters", APEC 1996, pp 152-158