Fault diagnosis of analog circuits with tolerances using artificial neural networks

IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Volumn , Issue , 2000, Pages 292-295

  Deng, Ying ^a   He, Yigang ^a   Sun, Yichuang ^b  

^a HUNAN UNIVERSITY   (China)

^b UNIVERSITY OF HERTFORDSHIRE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; MATHEMATICAL MODELS; NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS; PATTERN RECOGNITION;

ANALOG CIRCUITS; BACKWARD PROPAGATION; FAULT DIAGNOSIS; NETWORK TOPOLOGY;

SIGNAL PROCESSING;

EID: 0009600350     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. W. Bandler, "Fault diagnosis of analog circuits," Proceedings of IEEE, Vol.73, No.8, pp.1279-1325., 1985
2. R. W. Liu, ed., Testing and Diagnosis of Analog Circuits and Systems, Van Nostrand Reinhold, 1991.
3. Y. Sun and J. K. Fidler, "A topological method of class-fault diagnosis," Proc. IEEE Midwest Symp. on Circuits and Systems, Washington D C, USA, 1992.
4. Y. Sun, "Cut-fault diagnosis of nonlinear circuits," Proc. China Int. Conf. on Circuits and Systems, Nanjing, China, 1989.
5. R. Spina and S. Upadhyaya, "Fault diagnosis of analog circuits using artificial neural networks as signature analyzers," in Proc. Rochester Int. ASIC Conf., Sept, 1992, pp. 357-362
6. Y.G. He, X.J. Luo, G.Y. Qiu, A neural-based nonlinear L1-norm optimization algorithm for diagnosis of networks, J. of Electronics, Vol. 15,No.4, pp365-371,1998