Chaotic neuron models and their VLSI circuit implementations

IEEE Transactions on Neural Networks

Volumn 7, Issue 6, 1996, Pages 1339-1350

  Hsu, Charles C ^a,b   Gobovic, Desa ^a,c   Zaghloul, Mona E ^a,d   Szu, Harold H ^a,b  

^a IEEE

^b UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

^c MARSHALL UNIVERSITY   (United States)

^d George Washington University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0009554553     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/72.548163     Document Type: Article

References (21)

1. A. Rodriguez-Vazquez, J. L. Huertas, A. Rueda, B. Perez-Verdu, and L. O. Chua, "Chaos from switched-capacitor circuits: Discrete maps," Proc. IEEE, vol. 75, no. 8, pp. 1090-1106, Aug. 1987.
2. Y. Horio and K. Suyama, "Switched-capacitor chaotic neuron for chaotic neuron networks," in Proc. Int. Symp. Circuits Syst., Chicago, IL, 1993, pp. 1018-1021.
3. N. Kanou, Y. Horio, K. Aihara, and S. Nakamura, "A current-mode circuit of a chaotic neuron model," in Proc. 35th Midwest Symp. Circuits Syst., Washington, D.C., Aug. 1992, pp. 1530-1533.
4. H. Szu, B. Telfer, G. Rogers, D. Gobovic, C. Hsu, M. Zaghloul, and W. Freeman, "Spationtemporal chaos information processing in neural networks - Electronic implementation," in Proc. World Conf. Neural Networks, Portland, OR, July 1993, pp. 719-734.
5. C. C. Hsu, M. Zaghloul, and H. Szu, "CMOS circuit implementation to control chaotic neurons," in Proc. World Conf. Neural Networks, San Diego, CA, June 1994, pp. 684-689.
6. T. Matsumoto, L. O. Chua, and M. Komuro, "The double scroll," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 798-818, Aug. 1985.
7. T. Yamakawa, T. Miki, and E. Uchino, "A chaotic chip for analyzing nonlinear discrete dynamical network systems," in Proc. 2nd Int. Conf. Fuzzy Logic Neural Networks, Iizuka, Japan, July 1992, pp. 563-566.
8. K. Aihara, T. Takbe, and M. Toyoda, "Chaotic neural networks," Phys. Lett. A, vol. 144, nos. 6 and 7, pp. 333-340, Mar. 1990.
9. W. S. McCulloch and W. H. Pitts, Bull. Math. Biophys., vol. 5, p. 115, 1943.
10. E. R. Caianiello, "Outline of a theory of thought-process and thinking machines," J. Theoretical Biol., vol. 2, pp. 204-235, 1961.
11. J. Nagumo and S. Sato, "On a response characteristic of mathematical neuron model," Kybernetik, vol. 10, pp. 155-164, 1972.
12. D. Veitch, "Windows of stability in control chaos," IEEE Trans. Circuits Syst., vol. 38, pp. 808-819, Oct. 1992.
13. J. Baillieul, R. W. Brocket, and R. B. Washburn, "Chaotic motion in nonlinear feedback systems," IEEE Trans. Circuits Syst., vol. CAS-27, pp. 990-997, Nov. 1980.
14. T. Y. Li and J. A. Yorke, "Period three implies chaos," Amer. Math. Mon., vol. 82, pp. 985-992, 1985.
15. J. S. Nicolis, Chaos and Information Processing. Singapore: World, 1991.
16. C. C. Hsu, "Chaotic neural-network model and VLSI implementation," Ph.D. dissertation, Electr. Eng. Comput. Sci. Dep., George Washington Univ., Washington, D.C.
17. D. R. Frey, "Chaotic digital encoding: An appraoch to secure communication," IEEE Trans. Circuits Syst. II, vol. 40, pp. 660 666, Oct. 1993.
18. B. Baird, M. W. Hirsch, and F. Eeckman, "A neural-network associative memory for handwriting character recognition using mutliple Chua characters," IEEE Trans. Circuits Syst. II, vol. 40, pp. 667-674, Oct. 1993.
19. K. M. Cuomo, A. V. Oppenheim, and S. H. Strogatz, "Synchronization of erenz-based chaotic circuits with applications to communications," IEEE Trans. Circuits Syst. II, vol. 40, pp. 626-633, Oct. 1993.
20. H. Szu, C. Hsu, J. Dewitte, G. Moon, D. Gobovic, and M. Zaghloul, "Chaotic neurochip for fuzzy computing," Invited Paper, SPIE, San Diego, CA, vol. 2037-18, July 1993.
21. H. Szu, B. Telfer, G. Rogers, K. Lee, G. Moon, M. Zaghloul, and M. Loew, "Collective chaos in neural networks," in Proc. Int. Joint Conf. Neural Networks, IJCNN-92, Beijing, China, Nov. 1-6, 1992.