A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1999, Pages 1557-1560

  De Muer, B ^a   De Ranter, C ^a   Crols, J ^a,b   Steyaert, M ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b Ansem NV   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; CIRCUIT OSCILLATIONS; CMOS INTEGRATED CIRCUITS; ELECTRIC INDUCTORS; INTEGRATED CIRCUIT DESIGN; OSCILLATORS (ELECTRONIC); OSCILLISTORS; SIMULATED ANNEALING; VARIABLE FREQUENCY OSCILLATORS;

AUTOMATICALLY GENERATED; BI-CMOS PROCESS; INDUCTANCE EXTRACTION; LOW PHASE NOISE; OFFSET FREQUENCIES; QUALITY FACTORS; SIMULATED ANNEALING ALGORITHMS; SIMULATED ANNEALING OPTIMIZATION;

PHASE NOISE;

EID: 0006964397     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.814468     Document Type: Conference Paper

References (7)

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