Architecture of cell array neuro-processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1259, Issue , 1997, Pages 277-288

  Morishita, Takayuki ^a   Teramoto, Iwao ^a  

^a OKAYAMA PREFECTURAL UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION; CELLS; CYTOLOGY; NETWORK ARCHITECTURE;

BACKPROPAGATION LEARNING; CELL ARRAY; CONNECTION METHOD; CONTROL SEQUENCES; CONTROL UNIT; PROCESSOR ELEMENT; TYPICAL MODEL;

COMPUTER ARCHITECTURE;

EID: 0006654549     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63173-9_53     Document Type: Conference Paper

References (6)

1. Morishita, Т., and Teramoto, I.: Processing Cell Array Neural Network Multiprocessors proc. of IEEE International Conference on Neural Networks (1995) 1470-1473
2. Eldredge, J.G. and Hitchings, B.L.: RRANN: A Hardware Implementation of the Backpropagation Algorithm Using Reconfigur-able FPGAs. proc. of IEEE International Conference on Neural Networks (1994) 2097-2102
3. Morishita, Т., Tamura, Y., Satonaka, Т., Inoue, A., Katsu, S., and Otsuki, Т.: A Digital Neural Network Coprocessor with a Dynamically Reconfigurable Pipeline Architecture IEICE Trans. Electron., Vol.E76-C, No.7 (1993) 1191-1196.
4. Mauduit, N., Duranton, M., and Gobert, J.:"Lneuro 1.0: A Piece of Hardware LEGO for Building Neural Network Systems", IEEE Trans. Neural Network, Vol.3, No.3 (1992) 414-422
5. Fortes, J.A.B., and Wah, W. B.: "Systolic Arrays- From Concept to Implementation", IEEE Computer, 20, 7, (1987) 12-17.
6. Rumelhart, D.E., McClelland, J.L., and the PDP Research Group: Parallel Distributed Processing. MIT Press, Cambridge, 1986.