Modeling tunneling through ultra-thin gate oxides

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 1996, Pages 7-8

  Schenk, A ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

NUMERICAL METHODS; SCHRODINGER EQUATION;

ANALYTICAL FUNCTIONS; DEVICE SIMULATIONS; NUMERICAL INTEGRATIONS; NUMERICAL SOLUTION; TRAPEZOIDAL BARRIER; TUNNEL PROBABILITY; ULTRA THIN GATE OXIDE; WKB APPROXIMATIONS;

SEMICONDUCTOR DEVICES;

EID: 0006157525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.1996.865248     Document Type: Conference Paper

References (3)

1. H. Iwai, H. S. Momose, M. Saito, M. Ono, and Y. Katsumata. The Future of Ultra-Small-Geometry MOSFETs beyond 0.1 micron. Microelectronic Engineering, 28:147-154, 1995.
2. P. J. Price and J. M. Radcliffe. Esaki Tunneling. IBM Journal, Oct.:364-371, 1959.
3. K. H. Gundlach. Zur Berechnung des Tunnel-stroms durch eine trapezformige Potentialstufe. Solid-State Electronics, 9:949-57, 1966.