Influence of scribe lanes on wafer potentials and charging damage

Proceedings of the International Conference on Ion Implantation Technology

Volumn , Issue , 2000, Pages 569-572

  Lukaszek, Wes ^a  

^a Wafer Charging Monitors Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGING DAMAGE; IC MANUFACTURING; ION IMPLANT; J-V CHARACTERISTICS; ON-WAFER; SUBSTRATE POTENTIAL;

INTEGRATED CIRCUITS; SUBSTRATES;

ION IMPLANTATION;

EID: 0005969947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2000.924216     Document Type: Conference Paper

References (4)

1. Intl. Conf. on Ion Implant. Techn. 1998,2000
2. W. Lukaszek, M. Rendon, and D. Dyer, "Device Effects and Charging Damage: Correlations Between SPIDER-MEM and CHARM-2," 4th Intl. Symp. on Plasma Process-Induced Damage, pp. 200-203, 1999
3. J. Shideler, et al, "A New Technique for Solving Wafer Charging Problems," Semicond Intl., pp. 153-158, July 1995.
4. W. Lukaszek, Tech. Note 2, Wafer Charging Monitors, Inc.