A low-power concurrent multiplier-accumulator using conditional evaluation

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1999, Pages 629-633

  Bartlett, V A ^a   Grass, E ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY;

AVERAGE CASE; AVERAGE DELAY; CARRY-SAVE; DSP APPLICATION; LOW POWER; MULTIPLIER-ACCUMULATORS; TRANSISTOR LEVEL; TWO'S COMPLEMENT NUMBERS;

ENERGY UTILIZATION;

EID: 0005868472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.813186     Document Type: Conference Paper

References (11)

1. D. Kearney and N.W. Bergmann, "Bundled Data Asynchronous Multipliers with Data Dependent Computation Times", Proc. 3rd Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, pp. 186-197, 1997.
2. G.E. Sobelman and D. Raatz, "Low-power multiplier design using delayed evaluation", Proc. International Symposium on Circuits and Systems, pp. 1564-1567, 1995.
3. V.A. Bartlett and E. Grass, "A Self-Timed Multiplier using Conditional Evaluation", Proc. PATMOS'98, 8"" Int. Workshop on Power, Timing, Modeling, Optimization and Simulation, Lyngby, Denmark, pp.429-438, 1998.
4. E. Grass and S. Jones, "Activity-Monitoring Completion-Detection (AMCD): A new approach to achieve self-timing" Electronics Letters, Vol. 32, (2), pp.86-88, 1996.
5. V.A. Bartlett and E. Grass "Completion-Detection Technique for Dynamic Logic" Electronics Letters, Vol. 33, (22), pp. 1850-1852, 1997.
6. D.V. Poornaiah, R. Haribabu and M.O. Ahmad, "Design and VLSI Implementation of a Novel Concurrent 16-bit Multiplier-Accumulator for DSP Applications", Proc. International Conference on Acoustics, Speech and Signal Processing ICASSP-93, pp. 1:385-388, 1993.
7. S.B. Furber and J. Liu, "Dynamic Logic in Four-Phase Micropipelines", Proc. 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, pp.11-16, 1996.
8. C.R. Baugh and B.A. Wooley, "A Two's Complement Parallel Array Multiplication Algorithm" IEEE Trans, on Computers, Vol. C-22 No.12, pp.1045-1047, 1973.
9. M. Izumikawa et al., "A 0.25-nm CMOS 0.9-V 100-MHz DSP Core", IEEE Journal of Solid-Stale Circuits, Vol. SC-32, pp.52-61, 1997.
10. N. Weste and K. Eshraghian, "Principles of CMOS VLSI Design; a Systems Perspective" 2nd Edition. Addison-Wesley Publishing, Reading, MA, 1993.
11. A.P. Chandrakasan, and R.W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits" Proc. of the IEEE, Vol. 83, No.4, pp.498-523, 1995.