A study on a high blocking voltage UMOS-FET with a double gate structure

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn 1992-May, Issue , 1992, Pages 300-302

  Baba, Y ^a   Matsuda, N ^a   Yanagiya, S ^a   Hiraki, S ^a   Yasuda, S ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR);

BLOCKING VOLTAGE; DOUBLE GATE; DOUBLE-GATE STRUCTURES; DRAIN SOURCES; ON-RESISTANCE; SINGLE GATES; TRADE-OFF RELATIONSHIP; TRENCH DEPTH;

ECONOMIC AND SOCIAL EFFECTS;

EID: 0004418847     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPSD.1992.991291     Document Type: Conference Paper

References (3)

1. D. Ueda et al., IEEE-ED32 no. 1, p2, 1985
2. T. Wada et al., Proc. of 4th NASECODE, P108, 1985
3. I. Omura et al., Proc. of 6th NASECODE, p372, 1987