Simulation of high-speed single-electron memory

Extended Abstracts of 1998 6th International Workshop on Computational Electronics, IWCE 1998

Volumn 1998-October, Issue , 1998, Pages 17-20

  Mizuta, Hircishi ^a   Katayama, Kozo ^a   Muller, Heinz Olaf ^a   Williams, David ^a  

^a HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

IONIC CONDUCTION; STATIC RANDOM ACCESS STORAGE;

CELL STRUCTURE; HIGH SPEED; MOS-FET; SINGLE ELECTRON MEMORY; SPLIT GATES; SUBTHRESHOLD CHARACTERISTICS; WRITE OPERATIONS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0003685591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWCE.1998.742696     Document Type: Conference Paper

References (7)

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2. L. Gue, E. Leobandung and S. Chou, "A roomtemperature silicon single-electron metal-oxidesemiconductor memory with nanoscale floating-gate and ultranarrow channel", Appl. Phys. Lett. 70, 850, 1997.
3. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, "Room-temperature single-electron memory", IEEE Trans. on Electron Devices, ED41, 1628, 1994.
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5. H. Mizuta, D. Williams, K. Katayama, Heinz-Olaf Muller, and K. Nakazato, "High-speed single-electron memory: cell design and:architecture", Proc. of 2nd Znt. Workshop on Physics and Modeling of Devices based on Low-Dimensional Structures, Aizu-Wakamatsu, 1998.
6. K. Nakazato and J. White, "Single-electron switch for phase-locked single-electron logic devices", Proc. of IEDM 92, 487, 1992.
7. Heinz-Olaf Muller, K. Katayama, D. Williams and H. Mizuta, "Effects of disorder on the Blockade voltage of 2D quantum dot arrays", to be published in J. Appl. Phys. November 1998.