Hybrid instruction cache partitioning for preemptive real-time systems

Proceedings - Euromicro Conference on Real-Time Systems

Volumn , Issue , 1997, Pages 56-63

  Busquets Mataix, J V ^a   Serrano, J J ^a   Wellings, A ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE CONFIGURATIONS; HYBRID PARTITIONING; HYBRID TECHNIQUES; INSTRUCTION CACHES; SCHEDULABILITY ANALYSIS; WORST-CASE EXECUTION TIME;

CACHE MEMORY; INTERACTIVE COMPUTER SYSTEMS;

REAL TIME SYSTEMS;

EID: 0003652994     PISSN: 10683070     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMWRTS.1997.613764     Document Type: Conference Paper

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