From VHDL to efficient and first-timeright designs: A formal approach

ACM Transactions on Design Automation of Electronic Systems

Volumn 1, Issue 2, 1996, Pages 205-250

  Middelhoek, Peter F A ^a   Rajan, Sreeranga P ^b  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0003360169     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/233539.233541     Document Type: Article

References (79)

1. AELTEN, F. V., ALLEN, J., AND DEVADAS, S. 1994. Event-based verification of synchronous globally controlled, logic designs against signal flow graphs. IEEE Trans. CAD of ICs. 13, (Jan.) 122-134.
2. AHO, A. V., SETHI, R., AND ULLMAN, J. D. 1986. Compilers, Principles, Techniques, and Tools. Ch. 10, Addison Wesley, Reading, MA.
3. ANGELO, C. 1994. Formal hardware verification in a silicon compilation enviroment by means of theorem proving. PhD Thesis, IMEC, Leuven.
4. ASTHANA, P. 1995. Jumping the technology S-curve. IEEE Spectrum (June), 49-54.
5. BASILE, C., CAVALLERANO, A. P., AND DEISS, M. S. 1995. The U.S. HDTV standard: The grand alliance. IEEE Spectrum, 32, 4, (Apr) 36-45.
6. BRACE, K. S., RUDELL, R. L., AND BRYANT, R. E. 1990. Efficient implementation of a BDD package. In Proceedings of the 27th ACMI IEEE DAC, (June) 40-45.
7. BRAYTON, R. K, CAMPOSANO, R., DE MICHELI, G., OTTEN, R. H. J. M., AND VAN EIJNDHOVEN, J. T. J. 1988. The Yorktown Silicon Compiler System, D. Gajski, Ed. Addison-Wesley, Reading, MA.
8. BRODERSEN, R. W., Ed. 1992. Anatomy of a Silicon Compiler, Kluwer, Amsterdam.
9. CAMPOSANO, R. 1989. Behavior-preserving transformations for high-level synthesis. In Hardware Specification, Verification, and Synthesis: Mathematical Aspects, Cornell MSI Workshop, Lecture Notes in Computer Science 408, Springer-Verlag, New York, 106-128.
10. CAMPOSANO, R., AND TABET, R. M. 1989. Design representation for the synthesis of behavioral VHDL models. In Proceedings of the 9th International Conference on CHDL, J. A. Darringer and F. J. Ramming, Eds. Elsevier Science, Amsterdam, 49-58.
11. CHAIYAKUL, V., GAJSKI, D. D., AND RAMANCHANDRAN, L. 1993. High-level transformations for minimizing syntactic variances, In Proceedings ofDAC93, 413-418.
12. CHANDRAKASAN, A., POTKONJAK, M., RABAEY, J., AND BRODERSON, R. 1992. An approach for power minimization using transformations, In Proceedings of the IEEE VLSI Signal Processing Workshop, 41-50.
13. CHANDRAKASAN, A. P., POTKONJAK, M., MEHRA, R., RABAEY, J., AND BRODERSON, R. W. 1995. Optimizing power using transformations. In IEEE Trans. Comput. Aided Des. Int. Circuits Syst. 14, (Jan.) 12-31.
14. COMPUTER GENERAL ELECTRONIC DESIGN, 1990. The ELLA Language Reference Manual, The New Church, Henry St. Bath, U.K., Issue 4.0.
15. CYRLUK, D., RAJAN, S., SHANKAR, N., AND SRIVAS, M. 1994. Effective theorem proving for hardware verification. In Proceedings of the 2nd International Conference on Theorem Provers in Circuit Design, (Bad Heerenalb, Germany, Sept.), 26-29.
16. CYRLUK, D. 1993. Microprocessor Verification in PVS: A methodology and simple example, SRI-CSL-93-12, Tech. Rep. Computer Sci. Lab., SRI International, Menlo Park, CA, Dec.
17. DE MAN, H., RABAEY, J., Six, P., AND CLAESEN, L. 1986. Cathedral-II: A silicon compiler for digital signal processing. IEEE Des. Test 3, 6 (Dec.), 13-125.
18. ENGELEN, W., MIDDELHOEK, P. F. A., HUIJS, C., HOFSTEDE, J., AND KROL, T. 1993. Applying Software Transformations to SIL. SPRITE deliverable LS.a.5.2/UT/Y5/M6/lA, June.
19. EVEKING, H. 1987. Verification, synthesis and correctness-preserving transformations-Cooperative approaches to correct hardware design. In HDL Descriptions to (guaranteed Correct Circuit Designs, S. Borrione, Ed. Elsevier Science, Amsterdam.
20. FOURMAN, M. P. 1990. Formal system design, In Formal Methods for VLSI Design, J. Staunstrup, Ed. North-Holland, Amsterdam.
21. FRANSSEN, F., NACHTERGAELE, L., SAMSOM, H., CATTHOOR, F., AND DE MAN, H. 1994. Control flow optimization for fast system simulation and storage minimization, In Proceedings of EDTC 1994, (Paris, Feb.) 20-24.
22. GAJSKI, D. D., AND RAMACHANDRAN, L. 1994. Introduction to high-level synthesis. IEEE Des. Test Comput 11,4 (Winter).
23. HALLBERG, J., AND PENG, Z. 1995. Synthesis under local timing constraints in the CAMAD high-level synthesis system. In Proceedings of IEEE EUROMICRO 95 (Como, Italy, Sept. 4-7), 650-655.
24. HANNA, F. K., LONGLEY, M., AND DAECHE, N. 1990. Formal synthesis of digital systems. In Formal VLSI Specification and Synthesis. L. J. M. Claesen, Ed. VLSI Design Methods, I, Elsevier, New York.
25. HENNESSY, J. 1995. Hardware/software codesign of processors: Concepts and example, Lecture notes NATO/ASI course on hardware software co-design, part I, Tremezzo, Italy, June.
26. HlLFINGER, P. N. 1985. Silage: a high-level language and silicon compiler for digital signal processing. In Proceedings of IEEE Custom Integrated Circuits Conference, (Portland, OR, May) 213-216.
27. Huus, C., HOFSTEDE, J., AND KROL, T. 1992. SIL: a useful interface between specifications and silicon compilers. In Proceedings of the ProRISC/IEEE Workshop on CSSP (Houthalen, April) 99-104.
28. Huus, C., AND KROL, TH. 1994. A formal semantic model to fit SIL for transformational design. In Proceedings of 20th Euromicro Conference, (Liverpool, Sept.) 100-107.
29. IQBAL, Z., POTKONJAK, M., DEY, S., AND PARKER, A. 1993. Critical path minimization using retiming and algebraic speed-up. In Proceedings of DAC 93, (Dallas, TX, June 14-18) 573-577.
30. JANSSEN, G. 1993. ROBDD software. Dept. of Electrical Engineering, Technical Univ. of Eindhoven, Eindhoven, Netherlands, Oct.
31. JANSSEN, M., CATTHOOR, F., AND DE MAN, H. 1994. A specification invariant technique for operation cost minimisation in flow-graphs, In Proceedings of the Seventh International Symposium on High-Level Synthesis, (Niagara-on-the-Lake, Ontario, Canada, May 18-20) 146-151.
32. JOHNSON, S. D. 1984. Synthesis of Digital Designs from Recursion Equations. MIT Press, Cambridge, MA.
33. JONES, G., AND SHEERAN, M. 1990. Circuit design in Ruby, formal methods for VLSI design. (Summer School, Lyngby, Denmark, Sept.), North-Holland, Amsterdam.
34. JÖZWlAK, L. 1995. An efficient verification method for application in transformational design. In Proceedings of Euromicro 95, (Como, Italy, Sept.) 118-129.
35. KLOOSTERHUIS, W. E. H., EYCKMANS, M. M. R., HOFSTEDE, J., HUMS, G., KROL, TH., MCARDLE, O. P., SMITS, W. J. M., AND SVENSSON, L. G. L. 1993. SIL-2 language report. SPRITE deliverable LS.a.a/Philips/Y3-M12/2.
36. KLOOSTERHUIS, W. E. H., EYCKMANS, M. M. R., KROL, TH., MCARDLE, O. P., AND SMITS, W. J. M. 1993. SIL-2 language report. SPRITE deliverable LS.a.2/Philips/Y3-M12/l.
37. KROL, T., VAN MEERBERGEN, J., NIESSEN, C., SMITS, W., AND HUISKEN, J. 1992. The Sprite input language: An intermediate format for high-level synthesis. In Proceedings of EDAC 92, (Brussels, Mar.) 186-192.
38. KUNG, S. Y. 1988. VLSI Array Processors. Prentice Hall, Englewood Cliffs, NJ.
39. LEE, E. A., AND PARKS, T. M. 1995. Dataflow process networks. In Proceedings of the IEEE, 83, (May) 773-799.
40. LEE, M.H., KIM, J. H., LEE, J. S., RYU, K. K, AND SONG, D. I. 1994. A new algorithm for interlaced to progressive scan conversion based on directional correlations and its 1C design. IEEE Trans. Consumer Elec., 40, 2, (May) 119-125.
41. LINCOLN, P., OWRE, S., RUSHBY, J., SHANKAR, N., AND VON HENKE, F. 1993. Eight papers on formal verification. Tech. Rep. SRI-CSL-93-4, Computer Science Lab., SRI International, Menlo Park, CA, May.
42. LIPPENS, P. E. R., VAN MEERBERGEN, J. L., VAN DER WERF, A., VERHAEGH, W. F. J., MCSWEENEY, B. T., HUISKEN, J. O., AND MCARDLE, O. P. 1991. PHIDEO: A silicon compiler for high speed algorithms. In Proceedings of EDAC 91, (Amsterdam, Feb.) 436-441.
43. LOVEMAN, D. B. 1977. Program improvement by source-to-source transformations. J ACM, 24, 1, (Jan.) 121-145.
44. McFARLAND, M. C. 1993. Formal analysis of correctness of behavioral transformations. Formal Methods Syst. Des. 2, 3 (June), 231-257.
45. McFARLAND, M. C., AND PARKER, A. C. 1983. An abstract model of behavior for hardware descriptions. IEEE Trans. Comput. C-32, 7, (July) 621-636.
46. MEKENKAMP, G. E., MIDDELHOEK, P. F. A., MOLENKAMP, E., HOFSTEDE, J., AND KROL, TH. 1996. A Syntax based VHDL to CDFG translation model for high-level synthesis. In Proceedings of VHDL International Users Forum (VIUF) (Santa Clara, Feb. 28) 89-97.
47. MIDDELHOEK, P. F. A. 1994a. Transformational design of digital signal processing applications. In Proceedings of the ProRISC/IEEE Workshop on CSSP, (Arnhem, Netherlands, Mar.) 176-180.
48. MIDDELHOEK, P. F. A. 1994b. Transformational design of a direction detector for the progressive scan conversion processor. CS Memorandum 94-64, Univ. of Twente, Netherlands, Oct.
49. MIDDELHOEK, P. F. A. 1995. Arbitrary hardware software trade-offs. In Proceedings of the 6th IEEE International Workshop on Rapid Systems Prototyping, (Chapel Hill, NC, June) 19-25.
50. MIDDELHOEK, P. F. A. 1996. Transformations on loops and arrays. CS Memorandum 96, Univ. of Twente, Netherlands, to be published, 1996.
51. MIDDELHOEK, P. F. A., MEKENKAMP, G. E., MOLENKAMP, E., AND KROL, TH. 1995. A transformational approach to VHDL and CDFG based high-level synthesis: a case study. In Proceedings of the CICC 95, (Santa Clara, CA, May) 37-40.
52. DE MICHELI, G., Ku, D., MAILHOT, F., AND TRUONG, T. 1991. The Olympus synthesis system for digital design. Internal Report, Center for Integrated Systems, Stanford Univ., Stanford, CA.
53. MOLENKAMP, E., MEKENKAMP, G. E., HOFSTEDE, J., KROL, TH. 1995. SIL: an intermediate for syntax based VHDL synthesis. In Proceedings of the VIUF Spring 95, (San Diego, CA, Apr.) 5.5-5.9.
54. MUSGRAVE, G., AND HUGHES, R. B. 1995. Review of verification techniques. Lecture notes NATO/ASI course on hardware software codesign, part II, Tremezzo, Italy, June.
55. OWRE, S., SHANKAR, N., AND RUSHBY, J. M. 1993. User guide for the PVS specification and verification system, language, and proof checker (Beta release). Computer Science Laboratory, SRI International, Menlo Park, CA, Feb.
56. PENG, Z., KUCHCINSKI, K, AND LYLES, B. 1989. CAMAD: A unified data path/control synthesis environment, design methodologies for VLSI and computer architecture. D.A. Edwards, Ed. 53-67.
57. PENG, Z., AND KUCHCINSKI, K. 1994. Automated transformation of algorithms into registertransfer level implementations. IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 13, 2, 150-166.
58. PlGUET, C. 1989. Design methodologies and CAD tools. In Proceedings of the CICC 89 (San Diego, CA, May 15-19) 19.3.1-19.3.4.
59. POTKONJAK, M., AND RABAEY, J. 1994. Optimizing resource utilization using transformations. IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 13, 3 (Mar.).
60. PRESSMAN, R. S. 1992. Software Engineering: a Practitioner's Approach, 3rd Ed., McGrawHill, New York, 107.
61. RABAEY, J., AND HOANG, P. 1990. HYPER flowgraph policy, Version 1.2. Internal document Univ. of California, Berkeley, Mar.
62. RAJAN, S. P. 1995. Correctness of transformations in high-level synthesis. In Proceedings of the IFIP International Conference on CHDL (Chiba, Japan, Aug.) 597-603
63. RAJAN, S. P. 1995. Transformations on dependency graphs: Formal specification and efficient mechanical verification, PhD Thesis, Dept. of Computer Science, Univ. of British Columbia, Vancouver, Canada, Oct.
64. RAJAN, S. P., SHANKAR, N., AND SRIVAS, M. K. 1995. An integration of model-checking with automated proof checking. Lecture Notes in Computer Science, Vol. 939, P. Wolper, Ed. Springer-Verlag, Liege, Belgium, 84-97.
65. ROSSEN, L. 1990. Formal Ruby. Formal Methods for VLSI Design, J. Staunstrup, Ed., North-Holland, Amsterdam.
66. SAHRAOUI, Z., AND RIJNDERS, L. 1992. Report on the DIRDET experiments. Internal Report IMEC.
67. SAMSOM, H., CLAESEN, L., AND DE MAN, H. 1993. SynGuide: An environment for doing interactive correctness preserving transformations. In Proceedings of VLSI Signal Processing VI, L. D. J. Eggermont, P. Dewilde, E. Deprettere and J. van Meerbergen, Eds. IEEE, 269-277.
68. SAMSOM, H. 1995. Formal verification and transformation of video and image specifications, Ph.D. Thesis, IMEC/Univ. of Leuven.
69. SAMSOM, H., FRANSSEN, F., CATTHORR, F., AND DE MAN, H. 1994. Verification of loop transformations for real time signal processing applications. In Proceedings of VLSI Signal Processing VII (La Jolla, CA, Oct. 26-28), IEEE, 208-217.
70. SHANKAR, N., OWRE, S., AND RUSHBY, J. M. 1993. The PVS proof checker: A reference manual (Beta Release). Computer Science Laboratory, SRI International, Menlo Park, CA, Feb.
71. STOY, E., AND PENG, Z. 1994. A design representation for hardware/software co-synthesis. In Proceedings of IEEE Euromicro (Liverpool, Sept.) 192-199.
72. THOMAS, D., DIRKES, E. M., WALKER, R. A., RAJAN, J. V., NESTOR, J. A., AND BLACKBURN, R. L. 1988. The system architect's workbench. In Proceedings of the 25th ACM/IEEE Design Automation Conference, (Anaheim, CA, June 12-15) 337-343.
73. TIEDEMAN, W. D., LENK, S., GROBE, C., AND GRASS, W. 1993. Introducing structure into behavioral descriptions obtained from timing diagram specifications. In Proceedings of IEEE Euromicro 93, (Barcelona, Sept.).
74. VAN ROERMUND; A. H. M., SNIJDER, P. J., DIJKSTRA, H., HEMERYCK, G. G., HUIZER, G. M., SCHMITZ, J. M. P. SLNIJTER, R. J, 1989. A general-purpose programmable video signal processor. IEEE Trans, Cons. Elec., 35, 3, Aug., 249-258.
75. VEMURI, R. 1990. How to proof the completeness of a set of register level design transformations, In Proceedings of the 27th DAC, ACM/IEEE, June, 207-212.
76. THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1988. IEEE Standard VHDL Language Reference Manual, IEEE std. IEEE Press, New York. 1076-1088.
77. WALKER, R. A., AND CHAUDHURA, A. 1995. Introduction to the scheduling problem. IEEE Des. Test Comput 12, 2 (Summer), 60-69.
78. WALKER, R. A., AND THOMAS, D. E. 1989. Behavioral transformation for algorithmic level 1C design. IEEE Trans. CAD 8, 10 (Oct.), 1115-1128.
79. WOUDSMA, R., BEENKER, F., VAN MEERBERGEN, J., AND NIESSEN, C. 1990. Piramid: an architecture-driven silicon compiler for complex DSP applications. In Proceedings of IEEE International Symposium on Circuits and Systems, 2696-2700.