Instruction scheduling for TriMedia

Journal of Instruction-Level Parallelism

Volumn 1, Issue , 1999, Pages

  Hoogerbrugge, Jan ^a   Augusteijn, Lex ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Instruction scheduling; Register allocation; TriMedia; VLIW

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER AIDED DESIGN; DECODING; IMAGE PROCESSING; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SCHEDULING; TREES (MATHEMATICS);

DECISION TREES; FUNCTIONAL UNITS (FU); MEDIAPROCESSORS; TRIMEDIA;

MULTIMEDIA SYSTEMS;

EID: 0003360063     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (21)

1. G. A. Slavenburg, S. Rathnam, and H. Dijkstra, "The TriMedia TM-1 PCI VLIW Mediaprocessor," in Hot Chips 8, (Stanford, California), Aug. 1996.
2. J. Labrousse and G. A. Slavenburg, "CREATE-LIFE: A Modular Design Approach for High Performances ASIC's," in Proceedings of COMPCON '90, 1990.
3. J. Labrousse and G. A. Slavenburg, "A 50MHz Microprocessor with a Very Long Instruction Word Architecture," in Proceedings of ISSCC '90, Feb. 1990.
4. P. Y. T. Hsu and E. S. Davidson, "Highly Concurrent Scalar Processing," in Proceedings of the 13th Annual International Symposium on Computer Architecture, pp. 386-395, June 1986.
5. G. Sohi and M. Franklin, "High-Bandwidth Data Memory Systems for Superscalar Processors," in Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, (Santa Clara, California), pp. 53-62, 1991.
6. J. A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Transactions on Computers, vol. C-30, pp. 478-490, July 1981.
7. W. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter, R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab, J. G. Holm, and D. M. Lavery, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation," The Journal of Supercomputing, vol. 7, pp. 229-249, May 1993.
8. D. Bernstein and M. Rodey, "Global Instruction Scheduling for Superscalar Machines," in Proceedings of the SIGPLAN '91 Conference on Programming Language Design and Implementation, pp. 241-255, June 1991.
9. S. Banerjia, W. A. Havanki, and T. M. Conte, "Treegion Scheduling for Highly Parallel Processors," in Proceedings of the 3rd International Euro-Par Conference (Euro-Par '97), (Passau, Germany), pp. 1074-1078, Aug. 1997.
10. W. A. Havanki, S. Banerjia, and T. M. Conte, "Treegion Scheduling for Wide Issue Processors," in Proceedings of the 4th International Symposium on High-Performance Computer Architecture (HPCA-4), (Las Vegas), Feb. 1998.
11. J. A. Fisher, "Global Code Generation for Instruction-Level Parallelism: Trace Scheduling-2," Tech. Rep. HPL-93-43, Hewlett Packard Computer Systems Laboratory, Palo Alto, CA, June 1993.
12. P. G. Lowney, S. M. Freudenberger, T. J. Karzes, W. D. Lichtenstein, R. P. Nix, J. S. O'Donnell, and J. C. Ruttenberg, "The Multiflow Trace Scheduling Compiler," The Journal of Supercomputing, vol. 7, pp. 51-142, May 1993.
13. J. R. Allen, K. Kennedy, C. Porterfield, and J. D. Warren, "Conversion of Control Dependence to Data Dependence;" in Proceedings of the 10th ACM Symposium on Principles of Programming Languages, pp. 177-189, Jan. 1983.
14. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann, "Effective Compiler Support for Predicated Execution Using the Hyperblock," in Proceedings of the 25th Annual International Workshop on Microprogramming, (Portland, Oregon), pp. 45-54, Dec. 1992.
15. R. Cryton, J. Ferrante, B. K. Rosen, and M. N. Wegman, "An Efficient Method of Computing Static Single Assignment Form," in Proceedings of the 16th ACM SIGACT/SIGPLAN Symposium on Principles of Programming Languages, (Austin, Texas), pp. 23-25, Jan. 1989.
16. D. W. Wall, "Limits of Instruction-Level Parallelism," in Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 176-188, Apr. 1991.
17. J. R. Ellis, Bulldog: A Compiler for VLIW Architectures. ACM Doctoral Dissertation Awards, Cambridge, Massachusetts: MIT Press, 1986.
18. G. A. Slavenburg, TM1000 Databook. TriMedia Division, Philips Semiconductors, TriMedia Product Group, 811 E. Arques Avenue, Sunnyvale, CA 94088, www.trimedia.philips.com, 1997.
19. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows: Theory, Algorithms, and Applications. Prentice Hall, 1993.
20. D. M. Gillies, D. R. Ju, R. Johnson, and M. Schlansker, "Global Predicate Analysis and its Application to Register Allocation," in Proceedings of the 29th Annual International Workshop on Microprogramming, (Paris, France), pp. 114-125, Nov. 1996.
21. D. I. August, W. W. Hwu, and S. A. Mahlke, "A Framework for Balancing Control Flow and Predication," in Proceedings of the 30th Annual International Symposium on Microprogramming, (Research Triangle Park, North Carolina), pp. 92-103, Nov. 1997.