Analog DFT Using an Undersampling Technique

IEEE Design and Test of Computers

Volumn 16, Issue 4, 1999, Pages 84-88

  Mason, Ralph ^a   Ma, Shing ^b  

^a CARLETON UNIVERSITY   (Canada)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0003105573     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.808225     Document Type: Article

References (10)

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2. P. Fasang, "Analog/Digital ASIC Design for Testability," IEEE Trans. Industrial Electronics, May 1989, pp. 219-226.
3. IEEE, "IEEE P1149.4 Standard for a Mixed Signal Test Bus," Draft Prepared by the Mixed Signal Working Group, Test Technology Technical Committee, IEEE Computer Society, Sept. 1995.
4. K.P. Parker et al., "Structure and Methodology for an Analog Testability Bus," Proc. Int'l Test Conf., 1993, pp. 309-322.
5. A. Grebene, BiPolar and MOS Analog Integrated Circuit Design. New York: John Wiley & Sons, 1984.
6. C.L. Wey, "Built-in Self-Test (BIST) Structure for Analog Circuit Fault Diagnosis," IEEE Trans. Instrumentation and Measurement, vol. 39, no. 3, pp. 517-521, June 1990.
7. R. Groshong, "Undersampling Techniques Simplify Digital Radio," Electronic Design, pp. 67-78, 23 May 1991.
8. G. Hill, "The Benefits of Undersampling," Electronic Design, pp. 69-79, 11 July 1994.
9. J. Kirsten and T. Fleming, "Undersampling Reduces Data-Acquisition Costs for Select Applications, EDN, pp. 217-228, 21 June 1990.
10. M. Schwartz, Information Transmission, Modulation, and Noise. New York: McGraw-Hill, 1980.